From: Martin Prudek <prudemar@fel.cvut.cz>
Date: Wed, 15 Apr 2015 14:59:51 +0000 (+0200)
Subject: FPGA<->RPiSPI data frame extended from 96bits to 128bits
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/a54714b1caefa707bad771a992278d073b1377ee

FPGA<->RPiSPI data frame extended from 96bits to 128bits
---

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 1e06af9..9e60675 100644
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -161,7 +161,7 @@ architecture behavioral of rpi_mc_simple_dc is
 	signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
 	--signal pwm_in, pwm_dir_in: std_logic;
 	signal gpio_clk: std_logic;
-	signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
+	signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
 	signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
 	signal ce0_old: std_logic_vector(1 downto 0);
 	
@@ -299,6 +299,8 @@ begin
 	--pwm(2) <= '0';
 	--pwm(3) <= '0';
 	
+		
+	
 	process
 	begin
 		wait until (gpio_clk'event and gpio_clk='1');
@@ -329,11 +331,11 @@ begin
 			if (gpio7 = '0') then             -- SPI CS must be selected
 				-- shift serial data into dat_reg on each rising edge
 				-- of SCK, MSB first
-				dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
+				dat_reg(127 downto 0) <= dat_reg(126 downto 0) & gpio10;
 				end if;
 		elsif (spiclk_old="10" ) then --falling edge, faze zapisu
 			if (gpio7 = '0') then
-				gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
+				gpio9 <= dat_reg(127); --zapisujeme nejdriv MSB
 			end if;
 		end if;
 		
@@ -341,24 +343,24 @@ begin
 		--sestupna hrana SS, pripravime data pro prenos
 		if (ce0_old = "10" ) then 
 			income_data_valid<='0';
-			dat_reg(95 downto 64) <= position(31 downto 0); --pozice
-			dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
-			dat_reg(60 downto 58) <= pwm_en_p(1 to 3); --enable positive
-			dat_reg(57 downto 55) <= pwm_en_n(1 to 3); --shutdown
-			dat_reg(54 downto 49) <= pwm_match(1)(10 downto 5); --6 MSb of PWM1
-			dat_reg(48 downto 42) <= pwm_match(2)(10 downto 4); --7 MSb of PWM2
-			dat_reg(41 downto 36) <= pwm_match(3)(10 downto 5); --6 MSb of PWM3
-			dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
+			dat_reg(127 downto 96) <= position(31 downto 0); --pozice
+			dat_reg(95 downto 93) <= hal_in(1 to 3); --halovy sondy
+			dat_reg(92 downto 90) <= pwm_en_p(1 to 3); --enable positive
+			dat_reg(89 downto 87) <= pwm_en_n(1 to 3); --shutdown
+			dat_reg(86 downto 81) <= pwm_match(1)(10 downto 5); --6 MSb of PWM1
+			dat_reg(80 downto 74) <= pwm_match(2)(10 downto 4); --7 MSb of PWM2
+			dat_reg(73 downto 68) <= pwm_match(3)(10 downto 5); --6 MSb of PWM3
+			dat_reg(67 downto 32) <= adc_channels(35 downto 0); --current mesurments
 			adc_reset<='0'; --remove reset flag, and wait on its rising edge
 		elsif (ce0_old = "01") then --rising edge of SS, we should read the data
 			adc_reset<='1';
-			pwm_en_p(1 to 3)<=dat_reg(94 downto 92);
-			pwm_en_n(1 to 3)<=dat_reg(91 downto 89);
+			pwm_en_p(1 to 3)<=dat_reg(126 downto 124);
+			pwm_en_n(1 to 3)<=dat_reg(123 downto 121);
 			--11 bit pwm TODO: make it generic
-			pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(34 downto 24);
-			pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(23 downto 13);
+			pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(66 downto 56);
+			pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(55 downto 45);
 			-- 12 + 11 Unused
-			pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(10 downto 0);
+			pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(42 downto 32);
 			income_data_valid<='1';
 		end if;
 	end process;