From: Martin Prudek <prudemar@fel.cvut.cz>
Date: Wed, 15 Apr 2015 13:46:14 +0000 (+0200)
Subject: Project renamed 'to rpi_pmsm_control'.
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/6bf461a731b8241a4ed004c988ac1631638acf8d?hp=e9eadbd980bbd3a738745368c2e8acbe189b79b4

Project renamed 'to rpi_pmsm_control'.
---

diff --git a/pmsm-control/par.tcl b/pmsm-control/par.tcl
index 2cec468..d82da7b 100644
--- a/pmsm-control/par.tcl
+++ b/pmsm-control/par.tcl
@@ -1,7 +1,7 @@
 # designer SCRIPT:par.tcl LOGFILE:par.log
 
 # create a new design
-new_design -name "rpi_mc_simple_dc" -family "IGLOO"
+new_design -name "rpi_pmsm_control" -family "IGLOO"
 
 set_device \
     -die AGL125V5 \
@@ -16,7 +16,7 @@ set_device \
     -voltrange COM
 
 # set default back-annotation base-name
-set_defvar "BA_NAME" "rpi_mc_simple_dc_ba"
+set_defvar "BA_NAME" "rpi_pmsm_control_ba"
 
 # set working directory
 set_defvar "DESDIR" "par0"
@@ -29,7 +29,7 @@ set_defvar "BA_NETLIST_ALSO" "1"
 
 # setup status report options
 set_defvar "EXPORT_STATUS_REPORT" "1"
-set_defvar "EXPORT_STATUS_REPORT_FILENAME" "rpi_mc_simple_dc.rpt"
+set_defvar "EXPORT_STATUS_REPORT_FILENAME" "rpi_pmsm_control.rpt"
 
 # legacy audit-mode flags (left here for historical reasons)
 set_defvar "AUDIT_NETLIST_FILE" "1"
@@ -39,7 +39,7 @@ set_defvar "AUDIT_ADL_FILE" "1"
 
 # import of input files
 import_source  \
--format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" "syn0/rpi_mc_simple_dc.edn" \
+-format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" "syn0/rpi_pmsm_control.edn" \
 -format "pdc" "rpi_mc_1.pdc"
 
 # export translation of original netlist
@@ -62,9 +62,9 @@ compile \
     -report_high_fanout_nets_limit 10
 
 # auxiliary source files
-import_aux -format "sdc" "syn0/rpi_mc_simple_dc_sdc.sdc"
+import_aux -format "sdc" "syn0/rpi_pmsm_control_sdc.sdc"
 
-save_design rpi_mc_simple_dc.adb
+save_design rpi_pmsm_control.adb
 
 layout \
     -timing_driven \
@@ -74,11 +74,11 @@ layout \
     -route_incremental off \
     -placer_high_effort off
 
-save_design rpi_mc_simple_dc.adb
+save_design rpi_pmsm_control.adb
 
 export \
     -format bts_stp \
     -feature prog_fpga \
-    rpi_mc_simple_dc.stp
+    rpi_pmsm_control.stp
 
-save_design rpi_mc_simple_dc.adb
+save_design rpi_pmsm_control.adb
diff --git a/pmsm-control/program-agl.sh b/pmsm-control/program-agl.sh
index 4b1f0e2..a268dab 100755
--- a/pmsm-control/program-agl.sh
+++ b/pmsm-control/program-agl.sh
@@ -9,4 +9,4 @@ detect
 
 stapl prodlex.stp -aerase
 
-stapl rpi_mc_simple_dc.stp -aPROGRAM
+stapl rpi_pmsm_control.stp -aPROGRAM
diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
similarity index 100%
rename from pmsm-control/rpi_mc_simple_dc.vhdl
rename to pmsm-control/rpi_pmsm_control.vhdl
diff --git a/pmsm-control/syn.tcl b/pmsm-control/syn.tcl
index e8fb4cb..1a3a609 100644
--- a/pmsm-control/syn.tcl
+++ b/pmsm-control/syn.tcl
@@ -1,6 +1,6 @@
 # synplify_pro -licensetype synplifypro_actel -batch syn.tcl
 
-project -new rpi_mc_simple_dc
+project -new rpi_pmsm_control
 impl -name syn0
 
 #add_file pll50to200.vhd
@@ -12,7 +12,7 @@ add_file div8.vhdl
 add_file adc_reader.vhdl
 
 # top-level
-add_file rpi_mc_simple_dc.vhdl
+add_file rpi_pmsm_control.vhdl
 #add_file rpi_mc_simple_dc.sdc
 
 set_option -technology IGLOO