From: Pavel Pisa <ppisa@pikron.com>
Date: Fri, 1 May 2015 15:48:28 +0000 (+0200)
Subject: Change IRC recognition logic synchronous with main design clock.
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/5e9d551775408b98dd40058d4ba5ae0603cb3752?hp=5e9d551775408b98dd40058d4ba5ae0603cb3752

Change IRC recognition logic synchronous with main design clock.

Use of external, not synchronized signal event as
the trigger condition results in creation of additional
clock domain which can result in all kinds of hazard
conditions when used to manipulate with else synchronous
design state.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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