From: prudemar Date: Fri, 13 Feb 2015 10:43:50 +0000 (+0100) Subject: pridan podadresar pmsm-control X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/4122d986c4db1750a942225183f0b25f639e373c pridan podadresar pmsm-control --- diff --git a/pmsm-control/par.tcl b/pmsm-control/par.tcl new file mode 100644 index 0000000..2cec468 --- /dev/null +++ b/pmsm-control/par.tcl @@ -0,0 +1,84 @@ +# designer SCRIPT:par.tcl LOGFILE:par.log + +# create a new design +new_design -name "rpi_mc_simple_dc" -family "IGLOO" + +set_device \ + -die AGL125V5 \ + -package "100 VQFP" \ + -speed STD \ + -voltage 1.5 \ + -iostd LVTTL \ + -jtag yes \ + -probe yes \ + -trst yes \ + -temprange COM \ + -voltrange COM + +# set default back-annotation base-name +set_defvar "BA_NAME" "rpi_mc_simple_dc_ba" + +# set working directory +set_defvar "DESDIR" "par0" + +# set back-annotation output directory +set_defvar "BA_DIR" "par0" + +# enable the export back-annotation netlist +set_defvar "BA_NETLIST_ALSO" "1" + +# setup status report options +set_defvar "EXPORT_STATUS_REPORT" "1" +set_defvar "EXPORT_STATUS_REPORT_FILENAME" "rpi_mc_simple_dc.rpt" + +# legacy audit-mode flags (left here for historical reasons) +set_defvar "AUDIT_NETLIST_FILE" "1" +set_defvar "AUDIT_DCF_FILE" "1" +set_defvar "AUDIT_PIN_FILE" "1" +set_defvar "AUDIT_ADL_FILE" "1" + +# import of input files +import_source \ +-format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" "syn0/rpi_mc_simple_dc.edn" \ +-format "pdc" "rpi_mc_1.pdc" + +# export translation of original netlist +export -format "vhdl" "_map.vhdl" + +compile \ + -pdc_abort_on_error on \ + -pdc_eco_display_unmatched_objects off \ + -pdc_eco_max_warnings 10000 \ + -demote_globals off \ + -demote_globals_max_fanout 12 \ + -promote_globals off \ + -promote_globals_min_fanout 200 \ + -promote_globals_max_limit 0 \ + -localclock_max_shared_instances 12 \ + -localclock_buffer_tree_max_fanout 12 \ + -combine_register on \ + -delete_buffer_tree off \ + -delete_buffer_tree_max_fanout 12 \ + -report_high_fanout_nets_limit 10 + +# auxiliary source files +import_aux -format "sdc" "syn0/rpi_mc_simple_dc_sdc.sdc" + +save_design rpi_mc_simple_dc.adb + +layout \ + -timing_driven \ + -run_placer on \ + -place_incremental off \ + -run_router on \ + -route_incremental off \ + -placer_high_effort off + +save_design rpi_mc_simple_dc.adb + +export \ + -format bts_stp \ + -feature prog_fpga \ + rpi_mc_simple_dc.stp + +save_design rpi_mc_simple_dc.adb diff --git a/pmsm-control/prodlex.stp b/pmsm-control/prodlex.stp new file mode 100644 index 0000000..eb93a79 --- /dev/null +++ b/pmsm-control/prodlex.stp @@ -0,0 +1,1716 @@ +NOTE "CREATOR" "Designer Version: 9.1.0.18"; +NOTE "CAPTURE" "9.1.0.18"; +NOTE "DEVICE" "AGL250V2"; +NOTE "PACKAGE" "AGL250V2-vq100"; +NOTE "DATE" "2013/07/12"; +NOTE "TIME" "00:49:40"; +NOTE "STAPL_VERSION" "JESD71"; +NOTE "VENDOR" "Actel Corporation"; +NOTE "IDCODE" "03A141CF"; +NOTE "IDMASK" "06FFFFFF"; +NOTE "DESIGN" "prodlex"; +NOTE "DESIGN_DIRECTORY" "/home/marek/astro/pwccd/prodlex/"; +NOTE "CHECKSUM" "1643"; +NOTE "SECURITY" "Disable"; +NOTE "ALG_VERSION" "20"; +NOTE "MAP_VERSION" "1"; +NOTE "TOOL_VERSION" "1"; +NOTE "MAX_FREQ" "10000000"; +NOTE "SILSIG" "00000000"; +NOTE "TRACKING_SAR" "76713"; +NOTE "SPEED_GRAD" "STD"; +NOTE "TEMP_GRAD" "COM"; + +ACTION PROGRAM = + VERIFY_IDCODE, + SET_PRG_ARRAY, + W_INITIALIZE, + DO_ERASE, + DO_PROGRAM, + DO_VERIFY_BOL, + DO_PROGRAM_RLOCK, + DO_VERIFY_PGM_RLOCK, + DO_EXIT; +ACTION PROGRAM_ARRAY = + VERIFY_IDCODE, + SET_PRG_ARRAY, + AW_INITIALIZE, + DO_ERASE_ARRAY, + DO_PROGRAM, + DO_VERIFY_BOL, + DO_PROGRAM_RLOCK, + DO_VERIFY_PGM_RLOCK, + DO_EXIT; +ACTION ERASE_ARRAY = + VERIFY_IDCODE, + AW_INITIALIZE, + DO_ERASE_ARRAY_ONLY, + DO_EXIT; +ACTION ERASE = + VERIFY_IDCODE, + W_INITIALIZE, + DO_ERASE_ONLY, + DO_EXIT; +ACTION ERASE_ALL = + VERIFY_IDCODE, + INITIALIZE, + DO_ERASE_ALL, + DO_EXIT; +ACTION VERIFY = + VERIFY_IDCODE, + R_INITIALIZE, + DO_VERIFY_EOL, + DO_VERIFY_RLOCK, + DO_EXIT; +ACTION VERIFY_ARRAY = + VERIFY_IDCODE, + AR_INITIALIZE, + DO_VERIFY_EOL, + DO_VERIFY_RLOCK, + DO_EXIT; +ACTION READ_IDCODE = + DO_READ_IDCODE; +ACTION VERIFY_DEVICE_INFO = + VERIFY_IDCODE, + READ_INITIALIZE, + READ_IDCODE_ONLY, + DO_VERIFY_DEVICE_INFO, + DO_EXIT; +ACTION DEVICE_INFO = + VERIFY_IDCODE, + READ_INITIALIZE, + READ_IDCODE_ONLY, + DO_DEVICE_INFO, + DO_QUERY_SECURITY, + DO_EXIT; + + + +DATA CONSTBLOCK; + INTEGER IEEE1532=0; + INTEGER STAPL=1; + INTEGER DIRECTC=2; + INTEGER PDB=3; + INTEGER SVF=4; + INTEGER IAP=5; + INTEGER FP=0; + INTEGER FPLITE=1; + INTEGER FP3=2; + INTEGER SCULPTW=3; + INTEGER BPW=4; + INTEGER DIRECTCP=5; + INTEGER STP=6; + INTEGER FP4=7; + INTEGER FP33=0; + INTEGER FP34=1; + INTEGER FP40=2; + INTEGER FP41=3; + INTEGER FP42=4; + INTEGER FP50=5; + INTEGER FP51=6; + INTEGER FP60=7; + INTEGER FP61=8; + INTEGER FP62=9; + INTEGER FP84=11; + INTEGER FP85=12; + INTEGER FP86=13; + INTEGER FP90=14; + INTEGER FP91=15; + INTEGER UNKNOWN=127; + INTEGER UNSPECIFIED=0; + INTEGER QN132=1; + INTEGER VQ100=2; + INTEGER TQ144=3; + INTEGER PQ208=4; + INTEGER FG144=5; + INTEGER FG256=6; + INTEGER FG484=7; + INTEGER FG676=8; + INTEGER FG896=9; + INTEGER QN108=10; + INTEGER QN180=11; + INTEGER TQ100=12; + INTEGER CQ208=13; + INTEGER FG1152=14; + INTEGER BG456=15; + INTEGER UNDEFINED=63; + INTEGER GRADE_UNSPEC=0; + INTEGER GRADE_1=1; + INTEGER GRADE_2=2; + INTEGER GRADE_3=3; + INTEGER GRADE_F=4; + INTEGER GRADE_STD=5; + INTEGER GRADE_4=6; + INTEGER GRADE_UNDEF=7; +ENDDATA; + +DATA PARAMETERS; + INTEGER FREQ =4; +ENDDATA; + +DATA GV; + INTEGER ULOPT1_BITLOCATION =11; + INTEGER ULOPT0_BITLOCATION =10; + INTEGER ULUWE_BITLOCATION =9; + INTEGER ULARE_BITLOCATION =8; + INTEGER ULUPC_BITLOCATION =7; + INTEGER ULUFE_BITLOCATION =6; + INTEGER ULUFP_BITLOCATION =5; + INTEGER ULUFJ_BITLOCATION =4; + INTEGER ULFLR_BITLOCATION =3; + INTEGER ULULR_BITLOCATION =2; + INTEGER ULAWE_BITLOCATION =1; + INTEGER ULARD_BITLOCATION =0; + BOOLEAN BUFF128[128]; + BOOLEAN BUFF32[32]; + INTEGER I; + INTEGER J; + INTEGER TEMP; + INTEGER SDNUMBER; + INTEGER ROWNUMBER; + INTEGER DATAINDEX =0; + INTEGER FROMROWNUMBER =1; + INTEGER AESBLOCK; + BOOLEAN ID[32]; + BOOLEAN PASS = 1; + BOOLEAN FADDR[3]; + INTEGER STATUS =0; + BOOLEAN SILSIG[32] = $00000000; + BOOLEAN ISC_CONFIG_RESULT[18]; + BOOLEAN VERIFYEOL[2]; + BOOLEAN COMBERASESELECT[23]; + BOOLEAN SECKEY_OK = 1; + BOOLEAN SECREG[44]; + BOOLEAN ULUWE = 0; + BOOLEAN ULARE = 0; + BOOLEAN ULUPC = 0; + BOOLEAN ULUFE = 0; + BOOLEAN ULUFP = 0; + BOOLEAN ULUFJ = 0; + BOOLEAN ULFLR = 0; + BOOLEAN ULULR = 0; + BOOLEAN ULAWE = 0; + BOOLEAN ULARD = 0; + BOOLEAN ULOPT[2]; + BOOLEAN SUROWCHECKSUM[16]; + INTEGER SUROWCYCLECOUNT =0; + INTEGER ACT_UROW_CYCLE_COUNT =0; + BOOLEAN ACT_UROW_DESIGN_NAME[70] = $0102041d3fb266e98f; + BOOLEAN SUROWDESIGNNAME[70]; + BOOLEAN SUROWPROGMETHOD[3]; + BOOLEAN ACT_UROW_ALGO_VERSION[7] = $14; + BOOLEAN SUROWALGOVERSION[7]; + BOOLEAN SUROW_PKG_TYPE[6]; + BOOLEAN ACT_UROW_SW_VERSION[7]; + BOOLEAN SUROW_SW_VERSION[7]; + INTEGER PLAYERVERSIONVARIABLE =0; + INTEGER SCULPTORMAJORBASE =4; + INTEGER SCULPTORMINORBASE =50; + INTEGER PLAYER_VERSION_VARIABLE =0; + INTEGER SCULPTOR_MAJOR_BASE =4; + INTEGER SCULPTOR_MINOR_BASE =50; + BOOLEAN ACT_UROW_PROGRAM_SW[4] = $2; + BOOLEAN SUROWPROGRAMSW[4]; + BOOLEAN SUROW_SPEED_GRADE[3]; + BOOLEAN SUROW_SRAM_DISTURB[1]; + BOOLEAN ISERASEONLY = 0; + BOOLEAN ISRESTOREDESIGN = 0; + BOOLEAN FLAGDISPLAYCYC = 1; + BOOLEAN ISPRGARRAY = 0; + BOOLEAN BSRPATTERN[708] = $9249249249249249249249249249249249249249249249249 + 249249249249249249249249249249249249249249249249249249249249249249249249 + 24924924924924924924924924924924924924924924924924924924; + BOOLEAN SAMPLEMASK[708] = $0000000000000000000000000000000000000000000000000 + 000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000; + BOOLEAN BSR[708]; + BOOLEAN SAMPLE_DEVICE[708]; + BOOLEAN RLOCK[832] = $7fffffcffffffbfffffeffffffbfffffefffffffffffffffffff3f + ffffcffffff3fffffcffffff3fffffcffffff3fffffdffffff3fffffcffffff3fffffcff + ffff3fffffcffffff3fffffdffffffffffffffffffffffffffffffffffffffffffffffff + ffffffffff; + BOOLEAN ARRAYRONLY = 1; + BOOLEAN CHKARRAY = 0; + BOOLEAN FROMRONLY = 1; + BOOLEAN CHKFROM = 0; + BOOLEAN CHKNVM = 0; + BOOLEAN CHKSEC = 1; + BOOLEAN PERMLOCK = 0; + INTEGER HEX[16] = 70,69,68,67,66,65,57,56,55,54,53,52,51,50,49,48; + INTEGER NUMBEROFFROMROWS =8; + BOOLEAN INITIALIZE_DATA[5] = $00; + INTEGER SDTILE; + INTEGER NUMBEROFSDTILES =4; + INTEGER NUMBEROFMAPROWS =2300; + INTEGER IDREV; + INTEGER IDFAB; + INTEGER BM7DEVICE =0; + INTEGER BM1DEVICE =0; + BOOLEAN M1BUFF[128] = $acdd6548ccb488863e291eb18fe95077; + BOOLEAN M7BUFF[128] = $e137623a2eeee91126015f3f73664945; + BOOLEAN IDCODEVALUE[32] = $03a141cf; + BOOLEAN IDMASK[32] = $06ffffff; + INTEGER SECKEYCHK =0; + INTEGER DESIGNPKGTYPE =2; + BOOLEAN ACT_UROW_PROG_METHOD[3] = $1; + INTEGER LABEL_SEPARATOR =0; + INTEGER ROWITERATION =100; + INTEGER PAGEITERATION =100; + INTEGER PERCENT_UPDATE; + INTEGER DIFFERENCE; + INTEGER UNIQUEEXITCODE =0; +ENDDATA; + +DATA BITSTREAM; + BOOLEAN UROW[128]; + BOOLEAN UROW_MASK[128] = $fffffffffffffffffffffffffe01ffc0; + BOOLEAN DATASTREAM[1913600] = @WPw00000110040W0W000020G000400108002200000Wwc + qssso0000p@@lF999IjjjQp0000_@x@@IYaatcjj50000y_@@7HIIIORRRR36uXaa49jjTDq + WD2000y@@EH0vssMj90008@@z@69HIo000049IIICIII2Va00008III0HII2i134999H899f + 67Waaa4aaaKD020Za491aa8900gX7GIIIA0000800m0G0aaaa9mWauWku00000IIIIg1Vqss + sosssc3999A1000jjjQpjjPRMIYay0000tcjjbMjjj8III20000ORRR3RRRhWaaa3ZWQW3sO + RRssba897000mskJAGIIIYC000Wbaa8vIIaaJRpsEJYaaD9IIo4999sijjz8999B999fKHWj + jj19999aaaaGIII2QRRpIIIY4IIoQm6caaausssgZaa4PIIIdW0PRRRsIIIa600So88EH0II + IYxa1r72IF6WaaaySHGDW50IIIr07AK6KV8O0OGDuWIQ1r02AY4K3QeTDHDu22000r05w4Ae + ssscJIIIUy0ejjj2aaa84000G00e6GGhK1ijjjYaaa2d7K3w0JIIIkyWQW2qsssWjjjvIIIY + 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AiX_AgeWG3U8WJgY6OX@aHAEXFkV0ZAbkwLWI2Ev64200NMiKm9RS302P3uGE1AqK041FA3a + aiagtWW4a0LmZG0999fnH8g1u09B991FM2aaa4999AIGI2aaa4991992lOY6W0GIIG1r92W2 + 000G0G3jKHCCCL6W1n18nuHGTOG154Omj084T2GX6K1808W5TS8Q08w10YW7Lz8PSY50Y0Dk + 0f99PGg78P999uHj8899K302H3G0989e8Mj0GIGIq0N4aw91DS2404WfNEfJ0Aqsccm0000p + zzlF999IjjfQp0000URx@@IYaatcjj50000iD1Q0jjjD0000W@@VR2aWQ0C0yl@l3999Iijj + r0G0m@@@Q08G30001000_700ma000s20081000v300m80006000W8HIIYLRG209991899Lfn + 1Yaaa8aaaK3m189991999L3080C20gmO1a000W400I2u01000bPS0aaaa2GRe9456MqWQ021 + 100OD0AqGm1n9SWjjrIaij3IIIABDi0jvoIi4B9HIU000WRpss2hsMM499910000ijjjXijj + LGIIoU04K3G1sMaag101ibjjxEUW6000s000S900W1004d01S100a400i101IIIISJJ9nfjj + LdjjDxca49P4qaDRRrsURpssJYaaK8IoICRRRZQRRR8999Xba44qsscbssMjaaa8fIGa4ORN + 3020P995jjjL301I000C100mj000c500m4000P2008R000M34qG10DD9120481448u02Wsca + 4Y61TKM00e9f80Au213Waaq8200u3W3GIJI_501020G0000W9999uH22QmWe_QeYY5W0002a + W4O802aa40al01x0KWaaaiXGIe6W3G00G4om28001g1OXg6MeH23g1u00aaaT2eWA8IJC999 + IGI0U7e02QRW899XGG002000GfjjSh4A0ijDLaaaKu478sqs_aX3IGW0PRBa8991sam0raaa + O200wua00000OHII49000089H2QRhsmxJjT99IIisy@@sgjjZ6TRRYaaaGxx@FssssWijzPI + IIYm@@lVijDRpRRhGG0Y@@@Q080tosc899fQ0E0iljjHIII4@z@_PJIa4MIYaA9HIY@9IIs4 + 99Pz899Jaaa4xaaaWssscsttMPRRRsF9RrkjjPx_@LRlscjDMMijzsijj_ijjHFyG1OnssiD + ssglPRps6PhssORssMR_ssfPRRBORRRXjjjDkjjDpsssCsosimca8fsscjRJYaaRRssk9IIo + iPRR@A999cjjjNcEDC8241r1OGtgrUuBPeFLR2ST8a92W002w_de1O8uHKwyYdXXEeLSdIbw + Yq0s0110GUJA4Q031Qy422WWe1i86peYc_YespjGGq2k7jQ0MenlXQBmaMoM88LkY6GB0100 + n9S6880W88ARODS2quI100198anr1N4dWC2200Y8gCW0G0JJCHHE641XBZOOGQ0bKKu31E1L + i5O4dmI0200YKvdy9beJ0AG62IMnd222IIguh0acba12g2191fO@6f302WaWeK3G3WaaiYAC + gg3eule42e1hmdO8ZaTwUOZMFj8W6fY6Wi0quCmMPaWaaKHH2IGII2uKhe1s0898Pd0N0aaa + CG3XIGGX1roG100GW6l0GG08K02G000010400010W0020WW0r045; + INTEGER CHECKSUM =5699; +ENDDATA; + + +PROCEDURE DO_EXIT USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $81; + WAIT IDLE, 250 USEC; + IRSCAN 8, $81, CAPTURE BUFF128[7..0]; + IF ( ! (BUFF128[2]==0) ) THEN GOTO Label_0; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $07; + WAIT IDLE, 1 CYCLES; + WAIT IDLE, 200 USEC; + Label_0: + IRSCAN 8, $ff; + WAIT IDLE, 200 USEC; + WAIT RESET, 3 CYCLES; + EXIT STATUS; +ENDPROC; + +PROCEDURE DO_READ_SECURITY USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a4; + WAIT IDLE, 3 CYCLES; + DRSCAN 44, $00000000000, CAPTURE SECREG[]; + ULUWE = SECREG[ULUWE_BITLOCATION]; + ULARE = SECREG[ULARE_BITLOCATION]; + ULUPC = SECREG[ULUPC_BITLOCATION]; + ULUFE = SECREG[ULUFE_BITLOCATION]; + ULUFP = SECREG[ULUFP_BITLOCATION]; + ULUFJ = SECREG[ULUFJ_BITLOCATION]; + ULFLR = SECREG[ULFLR_BITLOCATION]; + ULULR = SECREG[ULULR_BITLOCATION]; + ULAWE = SECREG[ULAWE_BITLOCATION]; + ULARD = SECREG[ULARD_BITLOCATION]; + ULOPT[1] = SECREG[ULOPT1_BITLOCATION]; + ULOPT[0] = SECREG[ULOPT0_BITLOCATION]; +ENDPROC; + +PROCEDURE DO_OUTPUT_SECURITY USES GV; + PRINT "Security Settings :"; + IF ( ! (ULUFP==1) ) THEN GOTO Label_1; + PRINT "FlashROM Write/Erase protected by pass key."; + Label_1: + IF ( ! (ULUFJ==1) ) THEN GOTO Label_2; + PRINT "FlashROM Read protected by pass key."; + Label_2: + IF ( ! (ULAWE==1) ) THEN GOTO Label_3; + PRINT "Array Write/Erase protected by pass key."; + Label_3: + IF ( ! (ULARD==1) ) THEN GOTO Label_4; + PRINT "Array Verify protected by pass key."; + Label_4: + IF ( ! (ULUFE==1) ) THEN GOTO Label_5; + PRINT "Encrypted FlashROM Programming Enabled."; + Label_5: + IF ( ! (ULARE==1) ) THEN GOTO Label_6; + PRINT "Encrypted FPGA Array Programming Enabled."; + Label_6: + PRINT "========================================="; +ENDPROC; + +PROCEDURE DO_QUERY_SECURITY USES DO_READ_SECURITY,DO_OUTPUT_SECURITY; + CALL DO_READ_SECURITY; + CALL DO_OUTPUT_SECURITY; +ENDPROC; + +PROCEDURE READ_UROW USES BITSTREAM,GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a8; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 165 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE UROW[]; + SUROWALGOVERSION[6..0] = $00; + IF ( ! ( (UROW[5]==0)&&(UROW[0]==1)) ) THEN GOTO Label_7; + SUROWALGOVERSION[5..4] = UROW[24..23]; + Label_7: + IF ( ! ( (UROW[5]==1)&&(UROW[0]==0)) ) THEN GOTO Label_8; + SUROWALGOVERSION[5..4] = UROW[24..23]; + SUROWALGOVERSION[6] = 1; + Label_8: + SUROWCHECKSUM[15..0] = UROW[127..112]; + SUROWCYCLECOUNT = INT(UROW[111..102]); + SUROWDESIGNNAME[69..0] = UROW[101..32]; + SUROWPROGMETHOD[2..0] = UROW[31..29]; + SUROWALGOVERSION[3..0] = UROW[28..25]; + SUROW_PKG_TYPE[5..0] = UROW[22..17]; + SUROW_SW_VERSION[6..0] = UROW[16..10]; + SUROWPROGRAMSW[3..0] = UROW[9..6]; + SUROW_SRAM_DISTURB[0] = UROW[4]; + SUROW_SPEED_GRADE[2..0] = UROW[3..1]; + ACT_UROW_CYCLE_COUNT = SUROWCYCLECOUNT; +ENDPROC; + +PROCEDURE FIX_INT_ARRAYS USES GV; + IF ( ! (HEX[0]!=48) ) THEN GOTO Label_9; + FOR I = 0 TO 7; + TEMP = HEX[I]; + HEX[I] = HEX[(15-I)]; + HEX[(15-I)] = TEMP; + NEXT I; + Label_9: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DISP_CHKSUM_DESIGN USES GV,FIX_INT_ARRAYS; + CALL FIX_INT_ARRAYS; + IF ( ! (INT(SUROWCHECKSUM[15..0])==65535) ) THEN GOTO Label_10; + PRINT "CHECKSUM: "; + Label_10: + IF ( ! (INT(SUROWCHECKSUM[15..0])!=65535) ) THEN GOTO Label_11; + PRINT "CHECKSUM: ",CHR$(HEX[INT(SUROWCHECKSUM[15..12])]),CHR$(HEX[INT(SUROWCHECKSUM[11..8])]) + ,CHR$(HEX[INT(SUROWCHECKSUM[7..4])]),CHR$(HEX[INT(SUROWCHECKSUM[3..0])]); + Label_11: + IF ( ! ( ( (INT(SUROWDESIGNNAME[0..30])==2147483647)&&(INT(SUROWDESIGNNAME[31..61])==2147483647))&&(INT(SUROWDESIGNNAME[62..69])==255)) ) THEN GOTO Label_12; + PRINT "Design Name: "; + Label_12: + IF ( ! ( ( (INT(SUROWDESIGNNAME[0..30])!=2147483647)||(INT(SUROWDESIGNNAME[31..61])!=2147483647))||(INT(SUROWDESIGNNAME[62..69])!=255)) ) THEN GOTO Label_13; + PRINT "Design Name: ",CHR$(INT(SUROWDESIGNNAME[63..69])),CHR$(INT(SUROWDESIGNNAME[56..62])) + ,CHR$(INT(SUROWDESIGNNAME[49..55])),CHR$(INT(SUROWDESIGNNAME[42..48])),CHR$(INT(SUROWDESIGNNAME[35..41])) + ,CHR$(INT(SUROWDESIGNNAME[28..34])),CHR$(INT(SUROWDESIGNNAME[21..27])),CHR$(INT(SUROWDESIGNNAME[14..20])) + ,CHR$(INT(SUROWDESIGNNAME[7..13])),CHR$(INT(SUROWDESIGNNAME[0..6])); + Label_13: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DISPLAY_UROW USES BITSTREAM,CONSTBLOCK,GV,DISP_CHKSUM_DESIGN; + EXPORT "USER_ROW", UROW[127..0]; + PRINT "User information: "; + CALL DISP_CHKSUM_DESIGN; + IF ( ! (FLAGDISPLAYCYC==1) ) THEN GOTO Label_14; + PRINT "CYCLE COUNT: ",SUROWCYCLECOUNT; + Label_14: + INTEGER TMPINT =INT(SUROWPROGMETHOD[]); + INTEGER TMPINT2 =0; + INTEGER TMPINT3 =0; + INTEGER TMPINT4 =0; + INTEGER TMPINT5 =0; + IF ( ! (TMPINT==IEEE1532) ) THEN GOTO Label_15; + PRINT "Programming Method: IEEE1532"; + Label_15: + IF ( ! (TMPINT==STAPL) ) THEN GOTO Label_16; + PRINT "Programming Method: STAPL"; + Label_16: + IF ( ! (TMPINT==DIRECTC) ) THEN GOTO Label_17; + PRINT "Programming Method: DirectC"; + Label_17: + IF ( ! (TMPINT==PDB) ) THEN GOTO Label_18; + PRINT "Programming Method: PDB"; + Label_18: + IF ( ! (TMPINT==SVF) ) THEN GOTO Label_19; + PRINT "Programming Method: SVF"; + Label_19: + IF ( ! (TMPINT==IAP) ) THEN GOTO NOT_IAP; + PRINT "Progarmming Method: IAP"; + NOT_IAP: + PRINT "Algorithm Version: ",INT(SUROWALGOVERSION[6..0]); + TMPINT = INT(SUROW_PKG_TYPE[]); + IF ( ! (TMPINT==UNSPECIFIED) ) THEN GOTO Label_20; + PRINT "Device Package Type: package information not available from device"; + Label_20: + IF ( ! (TMPINT==QN132) ) THEN GOTO Label_21; + PRINT "Device Package Type: QN132/QNG132"; + Label_21: + IF ( ! (TMPINT==VQ100) ) THEN GOTO Label_22; + PRINT "Device Package Type: VQ100/VQG100"; + Label_22: + IF ( ! (TMPINT==TQ144) ) THEN GOTO Label_23; + PRINT "Device Package Type: TQ144/TQG144"; + Label_23: + IF ( ! (TMPINT==PQ208) ) THEN GOTO Label_24; + PRINT "Device Package Type: PQ208/PQG208"; + Label_24: + IF ( ! (TMPINT==FG144) ) THEN GOTO Label_25; + PRINT "Device Package Type: FG144/FGG144"; + Label_25: + IF ( ! (TMPINT==FG256) ) THEN GOTO Label_26; + PRINT "Device Package Type: FG256/FGG256"; + Label_26: + IF ( ! (TMPINT==FG484) ) THEN GOTO Label_27; + PRINT "Device Package Type: FG484/FGG484"; + Label_27: + IF ( ! (TMPINT==FG676) ) THEN GOTO Label_28; + PRINT "Device Package Type: FG676/FGG676"; + Label_28: + IF ( ! (TMPINT==FG896) ) THEN GOTO Label_29; + PRINT "Device Package Type: FG896/FGG896"; + Label_29: + IF ( ! (TMPINT==QN108) ) THEN GOTO Label_30; + PRINT "Device Package Type: QN108/QNG108"; + Label_30: + IF ( ! (TMPINT==QN180) ) THEN GOTO Label_31; + PRINT "Device Package Type: QN180/QNG180"; + Label_31: + IF ( ! (TMPINT==TQ100) ) THEN GOTO Label_32; + PRINT "Device Package Type: TQ100/TQG100"; + Label_32: + IF ( ! (TMPINT==CQ208) ) THEN GOTO Label_33; + PRINT "Device Package Type: CQ208/CQG208"; + Label_33: + IF ( ! (TMPINT==FG1152) ) THEN GOTO Label_34; + PRINT "Device Package Type: FG1152/FGG1152"; + Label_34: + IF ( ! (TMPINT==BG456) ) THEN GOTO Label_35; + PRINT "Device Package Type: BG456/BGG456"; + Label_35: + IF ( ! (TMPINT==UNDEFINED) ) THEN GOTO Label_36; + PRINT "Device Package Type: package information not available from device"; + Label_36: + TMPINT = INT(SUROW_SPEED_GRADE[]); + IF ( ! (TMPINT==GRADE_UNSPEC) ) THEN GOTO Label_37; + PRINT "Device Speed Grade: speed grade information not available from device"; + Label_37: + IF ( ! (TMPINT==GRADE_1) ) THEN GOTO Label_38; + PRINT "Device Speed Grade: -1"; + Label_38: + IF ( ! (TMPINT==GRADE_2) ) THEN GOTO Label_39; + PRINT "Device Speed Grade: -2"; + Label_39: + IF ( ! (TMPINT==GRADE_3) ) THEN GOTO Label_40; + PRINT "Device Speed Grade: -3"; + Label_40: + IF ( ! (TMPINT==GRADE_F) ) THEN GOTO Label_41; + PRINT "Device Speed Grade: -F"; + Label_41: + IF ( ! (TMPINT==GRADE_STD) ) THEN GOTO Label_42; + PRINT "Device Speed Grade: STD"; + Label_42: + IF ( ! (TMPINT==GRADE_4) ) THEN GOTO Label_43; + PRINT "Device Speed Grade: -4"; + Label_43: + IF ( ! (TMPINT==GRADE_UNDEF) ) THEN GOTO Label_44; + PRINT "Device Speed Grade: speed grade information not available from device"; + Label_44: + TMPINT = INT(SUROWPROGRAMSW[]); + IF ( ! (TMPINT==FP) ) THEN GOTO Label_45; + PRINT "Programmer: FlashPro"; + Label_45: + IF ( ! (TMPINT==FPLITE) ) THEN GOTO Label_46; + PRINT "Programmer: FlashPro Lite"; + Label_46: + IF ( ! (TMPINT==FP3) ) THEN GOTO Label_47; + PRINT "Programmer: FlashPro3"; + Label_47: + IF ( ! (TMPINT==FP4) ) THEN GOTO Label_48; + PRINT "Programmer: FlashPro4"; + Label_48: + IF ( ! (TMPINT==SCULPTW) ) THEN GOTO Label_49; + PRINT "Programmer: SiliconSculptor II"; + Label_49: + IF ( ! (TMPINT==BPW) ) THEN GOTO Label_50; + PRINT "Programmer: BP Programmer"; + Label_50: + IF ( ! (TMPINT==DIRECTCP) ) THEN GOTO Label_51; + PRINT "Programmer: DirectC"; + Label_51: + IF ( ! (TMPINT==STP) ) THEN GOTO Label_52; + PRINT "Programmer: Actel JAM Player"; + Label_52: + IF ( ! ( ( ( (TMPINT==FP)||(TMPINT==FPLITE))||(TMPINT==FP3))||(TMPINT==FP4)) ) THEN GOTO Label_68; + TMPINT2 = INT(SUROW_SW_VERSION[]); + IF ( ! (TMPINT2==FP33) ) THEN GOTO Label_53; + PRINT "Software: FlashPro v3.3"; + Label_53: + IF ( ! (TMPINT2==FP34) ) THEN GOTO Label_54; + PRINT "Software: FlashPro v3.4"; + Label_54: + IF ( ! (TMPINT2==FP40) ) THEN GOTO Label_55; + PRINT "Software: FlashPro v4.0"; + Label_55: + IF ( ! (TMPINT2==FP41) ) THEN GOTO Label_56; + PRINT "Software: FlashPro v4.1"; + Label_56: + IF ( ! (TMPINT2==FP42) ) THEN GOTO Label_57; + PRINT "Software: FlashPro v4.2"; + Label_57: + IF ( ! (TMPINT2==FP50) ) THEN GOTO Label_58; + PRINT "Software: FlashPro v5.0"; + Label_58: + IF ( ! (TMPINT2==FP51) ) THEN GOTO Label_59; + PRINT "Software: FlashPro v5.1"; + Label_59: + IF ( ! (TMPINT2==FP60) ) THEN GOTO Label_60; + PRINT "Software: FlashPro v6.0"; + Label_60: + IF ( ! (TMPINT2==FP61) ) THEN GOTO Label_61; + PRINT "Software: FlashPro v6.1"; + Label_61: + IF ( ! (TMPINT2==FP62) ) THEN GOTO Label_62; + PRINT "Software: FlashPro v6.2"; + Label_62: + IF ( ! (TMPINT2==FP84) ) THEN GOTO Label_63; + PRINT "Software: FlashPro v8.4"; + Label_63: + IF ( ! (TMPINT2==FP85) ) THEN GOTO Label_64; + PRINT "Software: FlashPro v8.5"; + Label_64: + IF ( ! (TMPINT2==FP86) ) THEN GOTO Label_65; + PRINT "Software: FlashPro v8.6"; + Label_65: + IF ( ! (TMPINT2==FP90) ) THEN GOTO Label_66; + PRINT "Software: FlashPro v9.0"; + Label_66: + IF ( ! (TMPINT2==FP91) ) THEN GOTO NOT_FP91; + PRINT "Software: FlashPro v9.1"; + NOT_FP91: + IF ( ! (TMPINT2==UNKNOWN) ) THEN GOTO Label_67; + PRINT "Software: FlashPro vX.X"; + Label_67: + LABEL_SEPARATOR = 0; + Label_68: + IF ( ! ( (TMPINT==SCULPTW)||(TMPINT==BPW)) ) THEN GOTO Label_72; + TMPINT3 = (INT(SUROW_SW_VERSION[6..5])+SCULPTORMAJORBASE); + TMPINT4 = (INT(SUROW_SW_VERSION[4..1])+SCULPTORMINORBASE); + TMPINT5 = 0; + IF ( ! (SUROW_SW_VERSION[0]==1) ) THEN GOTO Label_69; + TMPINT5 = 1; + Label_69: + IF ( ! (TMPINT==SCULPTW) ) THEN GOTO Label_70; + PRINT "Software: Sculptor Win v",TMPINT3,".",TMPINT4,".",TMPINT5; + Label_70: + IF ( ! (TMPINT==BPW) ) THEN GOTO Label_71; + PRINT "Software: BP Win v",TMPINT3,".",TMPINT4,".",TMPINT5; + Label_71: + LABEL_SEPARATOR = 0; + Label_72: + PRINT "========================================="; +ENDPROC; + +PROCEDURE READ_F_ROW USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $f9; + DRSCAN 3, FADDR[]; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $bf; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 165 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[]; +ENDPROC; + +PROCEDURE DO_DEVICE_INFO USES GV,READ_UROW,DISPLAY_UROW,READ_F_ROW; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0e; + WAIT IDLE, 1 CYCLES; + DRSCAN 32, $00000000, CAPTURE BUFF32[]; + EXPORT "SILSIG", BUFF32[]; + IRSCAN 8, $84, CAPTURE BUFF128[7..0]; + IF ( ! (BUFF128[2]==1) ) THEN GOTO CORE_NOT_ENABLED; + PRINT "FPGA Array is programmed and enabled."; + CORE_NOT_ENABLED: + IF ( ! (BUFF128[2]==0) ) THEN GOTO CORE_ENABLED; + PRINT "FPGA Array is not enabled."; + CORE_ENABLED: + CALL READ_UROW; + CALL DISPLAY_UROW; + FADDR[] = $0; + CALL READ_F_ROW; + EXPORT "FSN", BUFF128[55..8]; + PRINT "========================================="; +ENDPROC; + +PROCEDURE INIT_AES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $dd; + DRSCAN 128, $00000000000000000000000000000000; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 165 USEC; +ENDPROC; + +PROCEDURE DO_VERIFY_DEVICE_INFO USES GV,BITSTREAM,DO_EXIT,DO_READ_SECURITY,READ_UROW + ,DISP_CHKSUM_DESIGN; + CALL READ_UROW; + CALL DISP_CHKSUM_DESIGN; + CALL DO_READ_SECURITY; + BUFF32[31..0] = BOOL(CHECKSUM); + UROW[127..112] = BUFF32[15..0]; + UROW[101..32] = ACT_UROW_DESIGN_NAME[69..0]; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a8; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 165 USEC; + DRSCAN 128, $00000000000000000000000000000000,COMPARE UROW[],$ffff003fffffffffffffffff00000000 + ,PASS; + IF ( ! (PASS==0) ) THEN GOTO UROW_CMP_OK; + STATUS = -43; + PRINT "Failed to verify design information."; + UNIQUEEXITCODE = 32772; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + UROW_CMP_OK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE READ_IDCODE_ONLY USES GV; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0f; + WAIT IDLE, 1 CYCLES; + DRSCAN 32, $00000000, CAPTURE ID[]; + EXPORT "IDCODE", ID[]; +ENDPROC; + +PROCEDURE VERIFY_RLOCK USES GV; + IRSCAN 8, $84,COMPARE $04,$04,PASS; +ENDPROC; + +PROCEDURE DO_VERIFY_PGM_RLOCK USES GV,DO_EXIT,VERIFY_RLOCK; + CALL VERIFY_RLOCK; + IF ( ! (PASS==0) ) THEN GOTO RLOCK_PGM_PASS; + STATUS = 10; + PRINT "Failed to enable FPGA Array."; + UNIQUEEXITCODE = 32891; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + RLOCK_PGM_PASS: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_VERIFY_RLOCK USES GV,DO_EXIT,VERIFY_RLOCK; + CALL VERIFY_RLOCK; + IF ( ! (PASS==0) ) THEN GOTO RLOCK_VERIFY_PASS; + STATUS = 11; + PRINT "FPGA Array is not enabled."; + UNIQUEEXITCODE = 32892; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + RLOCK_VERIFY_PASS: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE VERIFY_ID_DMK USES GV,DO_EXIT,INIT_AES; + CALL INIT_AES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0a; + DRSCAN 128, M7BUFF[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 90 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[],COMPARE $c0000000000000000000000000000000 + ,$c0000000000000000000000000000000,PASS; + IF ( ! (BUFF128[127]==0) ) THEN GOTO M7VERDONE; + STATUS = -31; + PRINT "Failed to verify AES Sec."; + UNIQUEEXITCODE = 32775; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + M7VERDONE: + IF ( ! ( (BUFF128[126]==0)||(BM7DEVICE==0)) ) THEN GOTO MXIDOK; + IF ( ! ( (BUFF128[126]==1)&&(BM7DEVICE==0)) ) THEN GOTO LDETECTM1; + STATUS = 6; + PRINT "Failed to verify IDCODE."; + PRINT "Target is an M7 device."; + UNIQUEEXITCODE = 32776; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + LDETECTM1: + IF ( ! (BUFF128[126]==0) ) THEN GOTO Label_75; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0a; + DRSCAN 128, M1BUFF[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 90 USEC; + DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[],COMPARE $c0000000000000000000000000000000 + ,$c0000000000000000000000000000000,PASS; + IF ( ! (BUFF128[127]==0) ) THEN GOTO M1VERDONE; + STATUS = -31; + PRINT "Failed to verify AES Sec."; + UNIQUEEXITCODE = 32777; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + M1VERDONE: + BOOLEAN BTMPBUFFBIT126 = BUFF128[126]; + IF ( ! ( (BTMPBUFFBIT126==1)&&(BM1DEVICE==0)) ) THEN GOTO REGDEV; + STATUS = 6; + PRINT "Failed to verify IDCODE."; + PRINT "Target is an M1 device."; + UNIQUEEXITCODE = 32778; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + REGDEV: + IF ( ! ( (BTMPBUFFBIT126==0)&&(BM7DEVICE==1)) ) THEN GOTO Label_73; + STATUS = 6; + PRINT "Failed to verify IDCODE."; + PRINT "The Target is not an M7 Device."; + UNIQUEEXITCODE = 32781; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_73: + IF ( ! ( (BTMPBUFFBIT126==0)&&(BM1DEVICE==1)) ) THEN GOTO Label_74; + STATUS = 6; + PRINT "Failed to verify IDCODE."; + PRINT "The Target is not an M1 Device."; + UNIQUEEXITCODE = 32782; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_74: + LABEL_SEPARATOR = 0; + Label_75: + LABEL_SEPARATOR = 0; + MXIDOK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE VERIFY_IDCODE USES GV,PARAMETERS,DO_EXIT; + FREQUENCY (FREQ*1000000); + WAIT RESET, 5 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $0f; + DRSCAN 32, $00000000; + WAIT IDLE, 1 CYCLES; + DRSCAN 32, $00000000, CAPTURE ID[],COMPARE IDCODEVALUE[],IDMASK[],PASS; + IF ( ! (PASS==0) ) THEN GOTO IDOK; + STATUS = 6; + PRINT "Failed to verify IDCODE"; + UNIQUEEXITCODE = 32797; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + IDOK: + IDREV = INT(ID[31..28]); + IDFAB = INT(ID[24..24]); +ENDPROC; + +PROCEDURE IS_SECOK USES GV,DO_EXIT; + IF ( ! (SECKEY_OK==0) ) THEN GOTO SECOK; + STATUS = -35; + PRINT "Failed to match pass key."; + UNIQUEEXITCODE = 32799; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + SECOK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_CHECK_R USES GV,DO_EXIT,DO_READ_SECURITY; + CALL DO_READ_SECURITY; + IF ( ! (ULARE==1) ) THEN GOTO ARRAYEPR; + STATUS = -33; + PRINT "FPGA Array Encryption is enforced. Plain text verification is prohibited."; + UNIQUEEXITCODE = 32800; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + ARRAYEPR: + IF ( ! (ULARD==1) ) THEN GOTO SKIPRCHK1; + STATUS = -30; + PRINT "FPGA Array Verification is protected by pass key."; + PRINT "A valid pass key needs to be provided."; + UNIQUEEXITCODE = 32804; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + SKIPRCHK1: + IF ( ! (ULARD==0) ) THEN GOTO Label_76; + CHKSEC = 0; + Label_76: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_CHECK_W USES GV,DO_EXIT,DO_READ_SECURITY; + CALL DO_READ_SECURITY; + IF ( ! (ULAWE==1) ) THEN GOTO ARRAYWP; + STATUS = -28; + PRINT "FPGA Array Write/Erase is protected by pass key."; + PRINT "A valid pass key needs to be provided."; + UNIQUEEXITCODE = 32805; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + ARRAYWP: + IF ( ! (ULARD==1) ) THEN GOTO ARRAYRPW; + STATUS = -30; + PRINT "FPGA Array Verification is protected by pass key."; + PRINT "A valid pass key needs to be provided."; + UNIQUEEXITCODE = 32806; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + ARRAYRPW: + IF ( ! (ULARE==1) ) THEN GOTO ARRAYEPW; + STATUS = -33; + PRINT "FPGA Array Encryption is enforced. Plain text programming is prohibited."; + CALL DO_EXIT; + ARRAYEPW: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE BP_VER USES GV; + BOOLEAN PLAYER_VERSION_BOOLEAN[32]; + PLAYER_VERSION_BOOLEAN[31..0] = BOOL(PLAYERVERSIONVARIABLE); + INTEGER PLAYER_MAJOR_VERSION =(INT(PLAYER_VERSION_BOOLEAN[23..16])-SCULPTORMAJORBASE); + INTEGER PLAYER_MINOR_VERSION =(INT(PLAYER_VERSION_BOOLEAN[15..8])-SCULPTORMINORBASE); + ACT_UROW_SW_VERSION[6..5] = BOOL(PLAYER_MAJOR_VERSION); + ACT_UROW_SW_VERSION[4..1] = BOOL(PLAYER_MINOR_VERSION); + ACT_UROW_SW_VERSION[0] = PLAYER_VERSION_BOOLEAN[0]; +ENDPROC; + +PROCEDURE SET_PRG_ARRAY USES GV; + ISPRGARRAY = 1; +ENDPROC; + +PROCEDURE DO_INITIALIZE USES GV,DO_EXIT,READ_F_ROW,VERIFY_ID_DMK,DO_CHECK_R,DO_CHECK_W + ,BP_VER; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $7f; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 50 USEC; + BSR[707..0] = BSRPATTERN[707..0]; + BOOLEAN SHIFT_DATA[708]; + IRSCAN 8, $01; + DRSCAN 708, BSR[]; + WAIT IDLE, 1 CYCLES; + DRSCAN 708, SHIFT_DATA[], CAPTURE SAMPLE_DEVICE[]; + FOR I = 0 TO 707; + IF ( ! (SAMPLEMASK[I]==1) ) THEN GOTO Label_77; + BSR[I] = SAMPLE_DEVICE[I]; + Label_77: + LABEL_SEPARATOR = 0; + NEXT I; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $01; + DRSCAN 708, BSR[]; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $80; + DRSCAN 18, $00000; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 1875 USEC; + DRSCAN 18, $00000, CAPTURE ISC_CONFIG_RESULT[],COMPARE $30000,$30000,PASS; + IF ( ! (PASS==0) ) THEN GOTO CRCOK; + STATUS = 5; + PRINT "Failed to enter programming mode."; + EXPORT "ISC_Config_Result", ISC_CONFIG_RESULT[]; + UNIQUEEXITCODE = 32850; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + CRCOK: + FADDR[] = $0; + CALL READ_F_ROW; + EXPORT "FSN", BUFF128[55..8]; + CALL VERIFY_ID_DMK; + IF ( ! (CHKARRAY==1) ) THEN GOTO SKIPCHKARRAY; + IF ( ! (ARRAYRONLY==0) ) THEN GOTO Label_78; + CALL DO_CHECK_W; + Label_78: + IF ( ! (ARRAYRONLY==1) ) THEN GOTO Label_79; + CALL DO_CHECK_R; + Label_79: + LABEL_SEPARATOR = 0; + SKIPCHKARRAY: + IF ( ! (PLAYERVERSIONVARIABLE!=0) ) THEN GOTO Label_80; + CALL BP_VER; + Label_80: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE READ_INITIALIZE USES GV,DO_INITIALIZE; + CHKFROM = 0; + CHKARRAY = 0; + CHKNVM = 0; + CHKSEC = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE NW_INITIALIZE_COMMON USES GV; + CHKFROM = 0; + CHKARRAY = 0; +ENDPROC; + +PROCEDURE NW_INITIALIZE USES DO_INITIALIZE,NW_INITIALIZE_COMMON; + CALL NW_INITIALIZE_COMMON; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE NR_INITIALIZE_COMMON USES GV; + CHKFROM = 0; + CHKARRAY = 0; +ENDPROC; + +PROCEDURE NR_INITIALIZE USES DO_INITIALIZE,NR_INITIALIZE_COMMON; + CALL NR_INITIALIZE_COMMON; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE AW_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 0; + CHKFROM = 0; + CHKARRAY = 1; + CHKNVM = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE AR_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 1; + CHKFROM = 0; + CHKARRAY = 1; + CHKNVM = 0; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE W_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 0; + CHKARRAY = 1; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE R_INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 1; + CHKARRAY = 1; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE INITIALIZE USES GV,DO_INITIALIZE; + ARRAYRONLY = 0; + FROMRONLY = 0; + CHKFROM = 1; + CHKARRAY = 1; + CALL DO_INITIALIZE; +ENDPROC; + +PROCEDURE POLL_ERASE USES GV; + PASS = 0; + INTEGER ILOOP_0; + FOR ILOOP_0 = 262141 - 1 TO 0 STEP -1; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $84; + WAIT IDLE, 1 CYCLES; + WAIT IDLE, 1000 USEC; + DRSCAN 5, $00,COMPARE $00,$03,PASS; + IF PASS THEN ILOOP_0 = 0; + NEXT ILOOP_0; +ENDPROC; + +PROCEDURE POLL_PROGRAM USES GV; + INTEGER ILOOP_1; + FOR ILOOP_1 = 16381 - 1 TO 0 STEP -1; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $84; + WAIT IDLE, 1 CYCLES; + WAIT IDLE, 100 USEC; + DRSCAN 5, $00,COMPARE $00,$0b,PASS; + IF PASS THEN ILOOP_1 = 0; + NEXT ILOOP_1; +ENDPROC; + +PROCEDURE PROGRAM_UROW USES GV,BITSTREAM,DO_EXIT,POLL_PROGRAM; + FOR FROMROWNUMBER = NUMBEROFFROMROWS TO 1 STEP -1; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $9f; + DRSCAN 3, BOOL((FROMROWNUMBER-1)); + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $9b; + DRSCAN 128, $ffffffffffffffffffffffffffffffff; + WAIT IDLE, 5 CYCLES; + WAIT IDLE, 10000 USEC; + NEXT FROMROWNUMBER; + IF ( ! (ISERASEONLY==0) ) THEN GOTO SKIP_CYC_INCREMENT; + IF ( ! ( (ISPRGARRAY==1)&&(ACT_UROW_CYCLE_COUNT!=1023)) ) THEN GOTO Label_81; + ACT_UROW_CYCLE_COUNT = (ACT_UROW_CYCLE_COUNT+1); + Label_81: + LABEL_SEPARATOR = 0; + SKIP_CYC_INCREMENT: + IF ( ! (ISERASEONLY==1) ) THEN GOTO Label_82; + UROW[] = $ffffffffffffffffffffffffffffffff; + Label_82: + IF ( ! ( (ISERASEONLY==0)||(ISRESTOREDESIGN==1)) ) THEN GOTO SKIP_DESIGN_INFO; + BUFF32[31..0] = BOOL(CHECKSUM); + IF ( ! ( !ISRESTOREDESIGN) ) THEN GOTO Label_83; + UROW[127..112] = BUFF32[15..0]; + Label_83: + IF ( ! ISRESTOREDESIGN ) THEN GOTO Label_84; + UROW[127..112] = SUROWCHECKSUM[15..0]; + Label_84: + IF ( ! ( !ISRESTOREDESIGN) ) THEN GOTO Label_85; + UROW[101..32] = ACT_UROW_DESIGN_NAME[69..0]; + Label_85: + IF ( ! ISRESTOREDESIGN ) THEN GOTO Label_86; + UROW[101..32] = SUROWDESIGNNAME[69..0]; + Label_86: + LABEL_SEPARATOR = 0; + SKIP_DESIGN_INFO: + BUFF32[31..0] = BOOL(ACT_UROW_CYCLE_COUNT); + UROW[111..102] = BUFF32[9..0]; + UROW[31..29] = ACT_UROW_PROG_METHOD[2..0]; + UROW[28..25] = ACT_UROW_ALGO_VERSION[3..0]; + UROW[16..10] = ACT_UROW_SW_VERSION[6..0]; + UROW[9..6] = ACT_UROW_PROGRAM_SW[3..0]; + UROW[4] = SUROW_SRAM_DISTURB[0]; + IF ( ! (ACT_UROW_ALGO_VERSION[6]==1) ) THEN GOTO Label_87; + UROW[5] = 1; + UROW[0] = 0; + UROW[24..23] = ACT_UROW_ALGO_VERSION[5..4]; + Label_87: + IF ( ! (ACT_UROW_ALGO_VERSION[6]==0) ) THEN GOTO Label_88; + UROW[5] = 0; + UROW[0] = 1; + UROW[24..23] = ACT_UROW_ALGO_VERSION[5..4]; + Label_88: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a7; + DRSCAN 128, UROW[]; + WAIT IDLE, 15 CYCLES; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO PROGRAM_OK3; + STATUS = -24; + PRINT "Failed to program UROW"; + UNIQUEEXITCODE = 32853; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + PROGRAM_OK3: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $c0; + WAIT IDLE, 1 CYCLES; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $a8; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 165 USEC; + DRSCAN 128, $00000000000000000000000000000000,COMPARE UROW[],UROW_MASK[],PASS; + IF ( ! (PASS==0) ) THEN GOTO UROW_OK; + STATUS = -24; + PRINT "Failed to program UROW"; + UNIQUEEXITCODE = 32854; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + UROW_OK: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE FAIL_ERASE USES GV,DO_EXIT; + STATUS = 8; + PRINT "Failed Erase Operation"; + UNIQUEEXITCODE = 32855; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; +ENDPROC; + +PROCEDURE EXE_ERASE USES BITSTREAM,GV,READ_UROW,POLL_ERASE,PROGRAM_UROW,FAIL_ERASE; + IF ( ! (COMBERASESELECT[14]==1) ) THEN GOTO SKIPRUROW; + CALL READ_UROW; + EXPORT "ACTEL_SLOG_UROW", UROW[]; + SKIPRUROW: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $85; + DRSCAN 23, COMBERASESELECT[]; + WAIT IDLE, 3 CYCLES; + CALL POLL_ERASE; + IF ( ! (PASS==0) ) THEN GOTO ERASEOK; + CALL FAIL_ERASE; + ERASEOK: + IF ( ! (COMBERASESELECT[14]==1) ) THEN GOTO Label_89; + CALL PROGRAM_UROW; + Label_89: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_ERASE USES GV,EXE_ERASE; + PRINT "Erase ..."; + COMBERASESELECT[22..0] = $004000; + COMBERASESELECT[0] = 1; + CALL EXE_ERASE; + PRINT "Completed erase"; +ENDPROC; + +PROCEDURE DO_ERASE_ARRAY USES GV,EXE_ERASE; + PRINT "Erase FPGA Array ..."; + COMBERASESELECT[22..0] = $004001; + CALL EXE_ERASE; +ENDPROC; + +PROCEDURE DO_ERASE_ONLY USES GV,DO_ERASE; + ISERASEONLY = 1; + CALL DO_ERASE; +ENDPROC; + +PROCEDURE DO_ERASE_ARRAY_ONLY USES GV,DO_ERASE_ARRAY; + ISERASEONLY = 1; + CALL DO_ERASE_ARRAY; +ENDPROC; + +PROCEDURE DO_ERASE_ALL USES GV,EXE_ERASE; + IF ( ! ( (BM7DEVICE==1)||(BM1DEVICE==1)) ) THEN GOTO Label_90; + PRINT "Erase FPGA Array and FlashROM ..."; + Label_90: + IF ( ! ( (BM7DEVICE!=1)&&(BM1DEVICE!=1)) ) THEN GOTO Label_91; + PRINT "Erase FPGA Array, FlashROM and Security Settings ..."; + Label_91: + COMBERASESELECT[22..0] = $7fc00f; + ISERASEONLY = 1; + CALL EXE_ERASE; +ENDPROC; + +PROCEDURE LOAD_ROW_DATA USES BITSTREAM,GV; + FOR SDTILE = 1 TO NUMBEROFSDTILES; + FOR I = 1 TO 8; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $89; + DRSCAN 26, DATASTREAM[(DATAINDEX+25)..DATAINDEX]; + WAIT IDLE, 3 CYCLES; + DATAINDEX = (DATAINDEX+26); + NEXT I; + NEXT SDTILE; +ENDPROC; + +PROCEDURE EXE_PROGRAM USES GV,DO_EXIT,POLL_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $83; + WAIT IDLE, 3 CYCLES; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_92; + STATUS = 10; + PRINT "Failed to program FPGA array at row ",ROWNUMBER,"."; + UNIQUEEXITCODE = 32856; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_92: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE EXE_VERIFY USES GV,DO_EXIT,POLL_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $8d; + DRSCAN 2, VERIFYEOL[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_93; + STATUS = 11; + PRINT "Verify 0 failed at row ",ROWNUMBER,"."; + UNIQUEEXITCODE = 32857; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_93: + IRSCAN 8, $8d; + DRSCAN 2, VERIFYEOL[],COMPARE $0,$3,PASS; + IF ( ! (PASS==0) ) THEN GOTO Label_94; + STATUS = 11; + PRINT "Verify 0 failed at row ",ROWNUMBER,"."; + UNIQUEEXITCODE = 32858; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_94: + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $8e; + DRSCAN 2, VERIFYEOL[]; + WAIT IDLE, 3 CYCLES; + WAIT IDLE, 132 USEC; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_95; + STATUS = 11; + PRINT "Verify 1 failed at row ",ROWNUMBER,"."; + UNIQUEEXITCODE = 32859; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_95: + IRSCAN 8, $8e; + DRSCAN 2, VERIFYEOL[],COMPARE $0,$3,PASS; + IF ( ! (PASS==0) ) THEN GOTO Label_96; + STATUS = 11; + PRINT "Verify 1 failed at row ",ROWNUMBER,"."; + UNIQUEEXITCODE = 32860; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_96: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_PROGRAM USES GV,LOAD_ROW_DATA,EXE_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $2; + WAIT IDLE, 3 CYCLES; + PRINT "Programming FPGA Array"; + DATAINDEX = 0; + ROWNUMBER = (NUMBEROFMAPROWS-1); + INTEGER IREPEAT_0; + FOR IREPEAT_0 = NUMBEROFMAPROWS - 1 TO 0 STEP -1; + CALL LOAD_ROW_DATA; + CALL EXE_PROGRAM; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $3; + WAIT IDLE, 3 CYCLES; + IF ( ! ((ROWNUMBER%ROWITERATION)==0) ) THEN GOTO Label_97; + PERCENT_UPDATE = ((100*((NUMBEROFMAPROWS-ROWNUMBER)+1))/NUMBEROFMAPROWS); + DIFFERENCE = (PERCENT_UPDATE%10); + IF ( ! (DIFFERENCE>=5) ) THEN GOTO ROUND_DOWN_PGM_A; + PERCENT_UPDATE = (PERCENT_UPDATE+(10-DIFFERENCE)); + ROUND_DOWN_PGM_A: + IF ( ! (DIFFERENCE<5) ) THEN GOTO ROUND_UP_PGM_A; + PERCENT_UPDATE = (PERCENT_UPDATE-DIFFERENCE); + ROUND_UP_PGM_A: + EXPORT "PERCENT_DONE", PERCENT_UPDATE; + Label_97: + ROWNUMBER = (ROWNUMBER-1); + NEXT IREPEAT_0; +ENDPROC; + +PROCEDURE DO_VERIFY USES GV,LOAD_ROW_DATA,EXE_VERIFY; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $2; + WAIT IDLE, 3 CYCLES; + PRINT "Verifying FPGA Array"; + DATAINDEX = 0; + ROWNUMBER = (NUMBEROFMAPROWS-1); + INTEGER IREPEAT_1; + FOR IREPEAT_1 = NUMBEROFMAPROWS - 1 TO 0 STEP -1; + CALL LOAD_ROW_DATA; + CALL EXE_VERIFY; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $87; + DRSCAN 2, $3; + WAIT IDLE, 3 CYCLES; + IF ( ! ((ROWNUMBER%ROWITERATION)==0) ) THEN GOTO Label_98; + PERCENT_UPDATE = ((100*((NUMBEROFMAPROWS-ROWNUMBER)+1))/NUMBEROFMAPROWS); + DIFFERENCE = (PERCENT_UPDATE%10); + IF ( ! (DIFFERENCE>=5) ) THEN GOTO ROUND_DOWN_VER_ARRAY; + PERCENT_UPDATE = (PERCENT_UPDATE+(10-DIFFERENCE)); + ROUND_DOWN_VER_ARRAY: + IF ( ! (DIFFERENCE<5) ) THEN GOTO ROUND_UP_VER_ARRAY; + PERCENT_UPDATE = (PERCENT_UPDATE-DIFFERENCE); + ROUND_UP_VER_ARRAY: + EXPORT "PERCENT_DONE", PERCENT_UPDATE; + Label_98: + ROWNUMBER = (ROWNUMBER-1); + NEXT IREPEAT_1; + PRINT " Verifying FPGA Array -- pass"; +ENDPROC; + +PROCEDURE DO_VERIFY_BOL USES GV,DO_VERIFY; + VERIFYEOL[0] = 0; + CALL DO_VERIFY; +ENDPROC; + +PROCEDURE DO_VERIFY_EOL USES GV,DO_VERIFY; + VERIFYEOL[0] = 1; + CALL DO_VERIFY; +ENDPROC; + +PROCEDURE DO_PROGRAM_RLOCK USES GV,DO_EXIT,POLL_PROGRAM; + DATAINDEX = 0; + INTEGER IREPEAT_2; + FOR IREPEAT_2 = NUMBEROFSDTILES - 1 TO 0 STEP -1; + FOR I = 1 TO 8; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $89; + DRSCAN 26, RLOCK[(DATAINDEX+25)..DATAINDEX]; + WAIT IDLE, 3 CYCLES; + DATAINDEX = (DATAINDEX+26); + NEXT I; + NEXT IREPEAT_2; + IRSTOP IRPAUSE; + DRSTOP DRPAUSE; + IRSCAN 8, $8c; + WAIT IDLE, 3 CYCLES; + CALL POLL_PROGRAM; + IF ( ! (PASS==0) ) THEN GOTO Label_99; + STATUS = 10; + PRINT "Failed to enable FPGA Array."; + UNIQUEEXITCODE = 32862; + BUFF128[15..0] = BOOL(UNIQUEEXITCODE); + EXPORT "ERROR_CODE", BUFF128[15..0]; + CALL DO_EXIT; + Label_99: + LABEL_SEPARATOR = 0; +ENDPROC; + +PROCEDURE DO_READ_IDCODE USES READ_IDCODE_ONLY; + WAIT RESET, 5 CYCLES; + CALL READ_IDCODE_ONLY; + EXIT 0; +ENDPROC; + + +CRC A713; diff --git a/pmsm-control/program-agl.sh b/pmsm-control/program-agl.sh new file mode 100755 index 0000000..2af8b6c --- /dev/null +++ b/pmsm-control/program-agl.sh @@ -0,0 +1,11 @@ +#!/usr/local/bin/urjtag-i386 + +cable ft2232 vid=0x0403 pid=0x6010 + +debug detail + +detect + +stapl prodlex.stp -aerase + +stapl rpi_mc_simple_dc.stp -aPROGRAM diff --git a/pmsm-control/rpi_mc_1.pdc b/pmsm-control/rpi_mc_1.pdc new file mode 100644 index 0000000..42938a2 --- /dev/null +++ b/pmsm-control/rpi_mc_1.pdc @@ -0,0 +1,152 @@ +# +# rpi_mc_1 AGL125 +# +# Pavel Pisa +# Copyright PiKRON.com 2014 +# + +# +# IO banks setting +# +#set_iobank Bank3 -vcci 3.30 -fixed yes +#set_iobank Bank2 -vcci 3.30 -fixed yes +set_iobank Bank1 -vcci 3.30 -fixed yes +set_iobank Bank0 -vcci 3.30 -fixed yes + +# +# I/O constraints +# + +# RPi B+ P1 connector pins +# type LVTTL or LVCMOS33 + +# SDA +set_io {gpio2} -iostd LVCMOS33 -pinname 20 -fixed yes +# SCL +set_io {gpio3} -iostd LVCMOS33 -pinname 19 -fixed yes +# CLK +set_io {gpio4} -iostd LVCMOS33 -pinname 13 -fixed yes +# Tx +set_io {gpio14} -iostd LVCMOS33 -pinname 8 -fixed yes +# Rx +set_io {gpio15} -iostd LVCMOS33 -pinname 7 -fixed yes +# RTS +set_io {gpio17} -iostd LVCMOS33 -pinname 5 -fixed yes +# PWM0/PCMCLK +set_io {gpio18} -iostd LVCMOS33 -pinname 4 -fixed yes +# SD1DAT3 +set_io {gpio27} -iostd LVCMOS33 -pinname 3 -fixed yes +# SD1CLK +set_io {gpio22} -iostd LVCMOS33 -pinname 2 -fixed yes +# SD1CMD +set_io {gpio23} -iostd LVCMOS33 -pinname 98 -fixed yes +# SD1DAT0 +set_io {gpio24} -iostd LVCMOS33 -pinname 97 -fixed yes +# SPI0MOSI +set_io {gpio10} -iostd LVCMOS33 -pinname 96 -fixed yes +# SPI0MISO +set_io {gpio9} -iostd LVCMOS33 -pinname 95 -fixed yes +# SD1DAT1 +set_io {gpio25} -iostd LVCMOS33 -pinname 94 -fixed yes +# SPI0SCLK +set_io {gpio11} -iostd LVCMOS33 -pinname 93 -fixed yes +# SPI0CE0 +set_io {gpio8} -iostd LVCMOS33 -pinname 92 -fixed yes +# SPI0CE1 +set_io {gpio7} -iostd LVCMOS33 -pinname 91 -fixed yes +# GPCLK1 +set_io {gpio5} -iostd LVCMOS33 -pinname 84 -fixed yes +# GPCLK2 +set_io {gpio6} -iostd LVCMOS33 -pinname 83 -fixed yes +# PWM0 +set_io {gpio12} -iostd LVCMOS33 -pinname 82 -fixed yes +# PWM1 +set_io {gpio13} -iostd LVCMOS33 -pinname 81 -fixed yes +# PWM1/SPI1MISO/PCMFS +set_io {gpio19} -iostd LVCMOS33 -pinname 80 -fixed yes +# SPI1CE2 +set_io {gpio16} -iostd LVCMOS33 -pinname 79 -fixed yes +# SD1DAT2 +set_io {gpio26} -iostd LVCMOS33 -pinname 78 -fixed yes +# SPI1MOSI/PCMDIN/GPCLK0 +set_io {gpio20} -iostd LVCMOS33 -pinname 77 -fixed yes +# SPI1SCLK/PCMDOUT/GPCLK1 +set_io {gpio21} -iostd LVCMOS33 -pinname 76 -fixed yes + +# +# PWM +# +# Each PWM signal has cooresponding shutdown + +set_io {pwm[1]} -iostd LVCMOS33 -pinname 22 -fixed yes +set_io {shdn[1]} -iostd LVCMOS33 -pinname 21 -fixed yes +set_io {pwm[2]} -iostd LVCMOS33 -pinname 26 -fixed yes +set_io {shdn[2]} -iostd LVCMOS33 -pinname 23 -fixed yes +set_io {pwm[3]} -iostd LVCMOS33 -pinname 28 -fixed yes +set_io {shdn[3]} -iostd LVCMOS33 -pinname 27 -fixed yes + +# Fault/power stage status + +set_io {stat[1]} -iostd LVCMOS33 -pinname 29 -fixed yes +set_io {stat[2]} -iostd LVCMOS33 -pinname 30 -fixed yes +set_io {stat[3]} -iostd LVCMOS33 -pinname 31 -fixed yes + +# +# HAL inputs +# +set_io {hal_in[1]} -iostd LVCMOS33 -pinname 43 -fixed yes +set_io {hal_in[2]} -iostd LVCMOS33 -pinname 44 -fixed yes +set_io {hal_in[3]} -iostd LVCMOS33 -pinname 45 -fixed yes + +# +# IRC inputs +# +set_io {irc_a} -iostd LVCMOS33 -pinname 40 -fixed yes +set_io {irc_b} -iostd LVCMOS33 -pinname 41 -fixed yes +set_io {irc_i} -iostd LVCMOS33 -pinname 42 -fixed yes + +# +# Power status +# +set_io {power_stat} -iostd LVCMOS33 -pinname 32 -fixed yes + +# +# ADC for current +# +set_io {adc_miso} -iostd LVCMOS33 -pinname 33 -fixed yes +set_io {adc_mosi} -iostd LVCMOS33 -pinname 34 -fixed yes +set_io {adc_sclk} -iostd LVCMOS33 -pinname 35 -fixed yes +set_io {adc_scs} -iostd LVCMOS33 -pinname 36 -fixed yes + +# +# Extarnal SPI +# +set_io {ext_miso} -iostd LVCMOS33 -pinname 62 -fixed yes +set_io {ext_mosi} -iostd LVCMOS33 -pinname 61 -fixed yes +set_io {ext_sclk} -iostd LVCMOS33 -pinname 60 -fixed yes +set_io {ext_scs0} -iostd LVCMOS33 -pinname 59 -fixed yes +set_io {ext_scs1} -iostd LVCMOS33 -pinname 58 -fixed yes +set_io {ext_scs2} -iostd LVCMOS33 -pinname 57 -fixed yes + +# +# RS-485 Transceiver +# +set_io {rs485_rxd} -iostd LVCMOS33 -pinname 71 -fixed yes +set_io {rs485_txd} -iostd LVCMOS33 -pinname 69 -fixed yes +set_io {rs485_dir} -iostd LVCMOS33 -pinname 70 -fixed yes + +# +# CAN Transceiver +# +set_io {can_rx} -iostd LVCMOS33 -pinname 72 -fixed yes +set_io {can_tx} -iostd LVCMOS33 -pinname 73 -fixed yes + +# +# DIP switch +# +set_io {dip_sw[1]} -iostd LVCMOS33 -pinname 65 -fixed yes +set_io {dip_sw[2]} -iostd LVCMOS33 -pinname 64 -fixed yes +set_io {dip_sw[3]} -iostd LVCMOS33 -pinname 63 -fixed yes + +# Unused terminal to keep design tools silent +set_io {dummy_unused} -iostd LVCMOS33 -pinname 6 -fixed yes diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl new file mode 100644 index 0000000..c0c7d6d --- /dev/null +++ b/pmsm-control/rpi_mc_simple_dc.vhdl @@ -0,0 +1,161 @@ +-- +-- * LXPWR slave part * +-- common sioreg & common counter for several ADC&PWM blocks +-- +-- part of LXPWR motion control board (c) PiKRON Ltd +-- idea by Pavel Pisa PiKRON Ltd +-- code by Marek Peca +-- 01/2013 +-- +-- license: GNU GPLv3 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.util.all; + +entity rpi_mc_simple_dc is + port ( + gpio2: in std_logic; -- SDA + gpio3: in std_logic; -- SCL + gpio4: in std_logic; -- CLK + gpio14: in std_logic; -- Tx + gpio15: in std_logic; -- Rx + gpio17: in std_logic; -- RTS + gpio18: in std_logic; -- PWM0/PCMCLK + gpio27: in std_logic; -- SD1DAT3 + gpio22: in std_logic; -- SD1CLK + gpio23: out std_logic; -- SD1CMD + gpio24: out std_logic; -- SD1DAT0 + gpio10: in std_logic; -- SPI0MOSI + gpio9: in std_logic; -- SPI0MISO + gpio25: in std_logic; -- SD1DAT1 + gpio11: in std_logic; -- SPI0SCLK + gpio8: out std_logic; -- SPI0CE0 + gpio7: out std_logic; -- SPI0CE1 + gpio5: in std_logic; -- GPCLK1 + gpio6: in std_logic; -- GPCLK2 + gpio12: in std_logic; -- PWM0 + gpio13: in std_logic; -- PWM1 + gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS + gpio16: in std_logic; -- SPI1CE2 + gpio26: in std_logic; -- SD1DAT2 + gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0 + gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1 + -- + -- PWM + -- Each PWM signal has cooresponding shutdown + pwm: out std_logic_vector (1 to 3); + shdn: out std_logic_vector (1 to 3); + -- Fault/power stage status + stat: in std_logic_vector (1 to 3); + -- HAL inputs + hal_in: in std_logic_vector (1 to 3); + -- IRC inputs + irc_a: in std_logic; + irc_b: in std_logic; + irc_i: in std_logic; + -- Power status + power_stat: in std_logic; + -- ADC for current + adc_miso: in std_logic; + adc_mosi: in std_logic; + adc_sclk: in std_logic; + adc_scs: in std_logic; + -- Extarnal SPI + ext_miso: in std_logic; + ext_mosi: in std_logic; + ext_sclk: in std_logic; + ext_scs0: in std_logic; + ext_scs1: in std_logic; + ext_scs2: in std_logic; + -- RS-485 Transceiver + rs485_rxd: in std_logic; + rs485_txd: out std_logic; + rs485_dir: out std_logic; + -- CAN Transceiver + can_rx: in std_logic; + can_tx: in std_logic; + -- DIP switch + dip_sw: in std_logic_vector (1 to 3); + -- Unused terminal to keep design tools silent + dummy_unused : out std_logic + ); +end rpi_mc_simple_dc; + +architecture behavioral of rpi_mc_simple_dc is +attribute syn_noprune :boolean; +attribute syn_preserve :boolean; +attribute syn_keep :boolean; +attribute syn_hier :boolean; + -- Actel lib + -- component pll50to200 + -- port ( + -- powerdown, clka: in std_logic; + -- lock, gla: out std_logic + -- ); + -- end component; + -- component CLKINT + -- port (A: in std_logic; Y: out std_logic); + -- end component; + -- + signal pwm_in, pwm_dir_in: std_logic; + +-- attribute syn_noprune of gpio2 : signal is true; +-- attribute syn_preserve of gpio2 : signal is true; +-- attribute syn_keep of gpio2 : signal is true; +-- attribute syn_hier of gpio2 : signal is true; + +begin +-- PLL as a reset generator +-- copyclk: CLKINT +-- port map ( +-- a => clkm, +-- y => pll_clkin); +-- pll: pll50to200 +-- port map ( +-- powerdown => '1', +-- clka => pll_clkin, +-- gla => pll_clkout, +-- lock => pll_lock); +-- -- reset <= not pll_lock; +-- reset <= '0'; -- TODO: apply reset for good failsafe + -- upon power-on +-- clock <= clkm; + + dummy_unused <= gpio2 and gpio3 and gpio4 and + gpio5 and gpio6 and gpio9 and + gpio10 and gpio11 and gpio12 and gpio13 and gpio14 and + gpio15 and gpio16 and gpio17 and gpio19 and + gpio20 and gpio21 and + gpio25 and gpio26 and gpio27 and + stat(1) and stat(2) and stat(3) and + hal_in(1) and hal_in(2) and hal_in(3) and + irc_i and power_stat and adc_miso and adc_mosi and adc_sclk and adc_scs and + ext_miso and ext_mosi and ext_sclk and ext_scs0 and ext_scs1 and ext_scs2 and + rs485_rxd and + can_rx and can_tx and + dip_sw(1) and dip_sw(2) and dip_sw(3); + + rs485_txd <= '1'; + rs485_dir <= '0'; + + gpio23 <= irc_a; + gpio24 <= irc_a; + + gpio7 <= irc_b; + gpio8 <= irc_b; + + pwm_in <= gpio18; + pwm_dir_in <= gpio22; + + shdn(1) <= '0'; + shdn(2) <= '0'; + shdn(3) <= '1'; + + pwm(1) <= pwm_in and not pwm_dir_in; + pwm(2) <= pwm_in and pwm_dir_in; + pwm(3) <= '0'; + +end behavioral; diff --git a/pmsm-control/syn.tcl b/pmsm-control/syn.tcl new file mode 100644 index 0000000..2d12ea8 --- /dev/null +++ b/pmsm-control/syn.tcl @@ -0,0 +1,21 @@ +# synplify_pro -licensetype synplifypro_actel -batch syn.tcl + +project -new rpi_mc_simple_dc +impl -name syn0 + +#add_file pll50to200.vhd +add_file util.vhdl + +# top-level +add_file rpi_mc_simple_dc.vhdl +#add_file rpi_mc_simple_dc.sdc + +set_option -technology IGLOO +set_option -part AGL250V5 +set_option -package VQFP100 +set_option -speed_grade std + +set_option -frequency 40.0 + +project -run +project -save diff --git a/pmsm-control/synthetize-agl.sh b/pmsm-control/synthetize-agl.sh new file mode 100755 index 0000000..872622a --- /dev/null +++ b/pmsm-control/synthetize-agl.sh @@ -0,0 +1,4 @@ +#!/bin/sh + +synplify_pro -licensetype synplifypro_actel -batch syn.tcl || exit 1 +designer SCRIPT:par.tcl LOGFILE:par.log || exit 1 diff --git a/pmsm-control/util.vhdl b/pmsm-control/util.vhdl new file mode 100644 index 0000000..a8bfa98 --- /dev/null +++ b/pmsm-control/util.vhdl @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package util is + -- ceil(log2(n)) + function ceil_log2(n: natural) return natural; + -- ceil(a/b) + function ceil_div(a: integer; b: integer) return integer; + -- + function max(left, right: integer) return integer; + function min(left, right: integer) return integer; +end; + +--- + +package body util is + + function ceil_log2(n: natural) return natural is + begin + if n <= 1 then + return 0; + else + if n mod 2 = 0 then + return 1 + ceil_log2(n/2); + else + return 1 + ceil_log2((n+1)/2); + end if; + end if; + end function ceil_log2; + + function ceil_div(a: integer; b: integer) return integer is + begin + return (a+b-1)/b; + end function ceil_div; + + function max(left, right: integer) return integer is + begin + if left > right then return left; + else return right; + end if; + end; + + function min(left, right: integer) return integer is + begin + if left < right then return left; + else return right; + end if; + end; + +end util;