From: Martin Prudek <prudemar@fel.cvut.cz>
Date: Wed, 25 Mar 2015 19:13:55 +0000 (+0100)
Subject: otestovan 'spi repeater' neuplny zpetny prenos (chybny prvni a posledni byte). Je... 
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/3195d1e08e675b2a7a5b70c8b276eb825abf77c8

otestovan 'spi repeater' neuplny zpetny prenos (chybny prvni a posledni byte). Je treba ale pridat udalost na falling edge CS. Pouzivan CPHA=0 CPOL=0 (spi mod 0)
---

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index f3ca087..d1810c6 100644
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -29,7 +29,7 @@ entity rpi_mc_simple_dc is
 		gpio23: out std_logic; -- SD1CMD
 		gpio24: out std_logic; -- SD1DAT0
 		gpio10: in std_logic; -- SPI0MOSI
-		gpio9: in std_logic; -- SPI0MISO
+		gpio9: out std_logic; -- SPI0MISO
 		gpio25: out std_logic; -- SD1DAT1
 		gpio11: in std_logic; -- SPI0SCLK
 		gpio8: in std_logic; -- SPI0CE0
@@ -104,7 +104,7 @@ architecture behavioral of rpi_mc_simple_dc is
 
 	signal pwm_in, pwm_dir_in: std_logic;
 	signal spi_clk: std_logic;
-	signal dat_reg : STD_LOGIC_VECTOR (7 downto 0); --registr pro SPI
+	signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
 
 	--  attribute syn_noprune of gpio2 : signal is true;
 	--  attribute syn_preserve of gpio2 : signal is true;
@@ -143,7 +143,7 @@ begin
 		dip_sw(1) and dip_sw(2) and dip_sw(3) and
 		irc_a and irc_b and
 		-- gpio17 and gpio18 and gpio27 and gpio22 and
-		gpio8 and gpio9 and gpio11 and gpio7 and gpio10 and
+		gpio8  and gpio11 and gpio7 and gpio10 and
 		ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
 			
 	rs485_txd <= '1';
@@ -181,6 +181,10 @@ begin
 				gpio25 <= dat_reg(0);
 	
 			end if;
+		elsif (falling_edge(spi_clk)) then
+			if (gpio7 = '0') then
+				gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
+			end if;
 		end if;
 	end process;
 end behavioral;