From: Pavel Pisa <ppisa@pikron.com>
Date: Fri, 1 May 2015 14:59:49 +0000 (+0200)
Subject: Include in PMSM design to implement safe behavior when external clocks are not present.
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/24df44d1c49bcb0f29f43f577ef3d245bced9e28?ds=sidebyside;hp=24df44d1c49bcb0f29f43f577ef3d245bced9e28

Include in PMSM design to implement safe behavior when external clocks are not present.

The PLL is configured to synthesize 200 MHz clock from 50 MHz input.
The clock monitor holds PWM outputs low if the external clocks are
not present. The reference lost is recognized 6 in 8 cycles
of 200 MHz synthesized clock as well.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
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