From: Martin Prudek <prudemar@fel.cvut.cz>
Date: Sat, 4 Apr 2015 16:55:12 +0000 (+0200)
Subject: Unused CLKINT for SCLK removed.
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/commitdiff_plain/14413009e194a96bcbb16cd456a7cd9f3a3e2ca4

Unused CLKINT for SCLK removed.
---

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index c447118..6b5dd4b 100644
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -115,7 +115,6 @@ architecture behavioral of rpi_mc_simple_dc is
 
 	signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
 	signal pwm_in, pwm_dir_in: std_logic;
-	signal spi_clk: std_logic;
 	signal gpio_clk: std_logic;
 	signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
 	signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
@@ -129,13 +128,6 @@ architecture behavioral of rpi_mc_simple_dc is
 begin
 	-- PLL as a reset generator
 	
-	--zesileni signalu hodin SPI - bez zesileni nelze syntetizovat
-	copyclk: CLKINT
-	port map (
-		a => gpio11,
-		y => spi_clk
-	);
-	
 	--zesileni signalu GPIO CLK
 	copyclk2: CLKINT
 	port map (
@@ -206,9 +198,11 @@ begin
 		--position is obtained on rising edge -> we should write it on falling edge
 		wait until (gpio_clk'event and gpio_clk='0');
 		
-		spiclk_old(0)<=spi_clk;
+		--SCLK edge detection
+		spiclk_old(0)<=gpio11;
 		spiclk_old(1)<=spiclk_old(0);
 		
+		--SS edge detection
 		ce0_old(0)<=gpio7;
 		ce0_old(1)<=ce0_old(0);