GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for...
authorMartin Prudek <prudemar@fel.cvut.cz>
Sat, 11 Apr 2015 09:14:13 +0000 (11:14 +0200)
committerMartin Prudek <prudemar@fel.cvut.cz>
Sat, 11 Apr 2015 09:14:13 +0000 (11:14 +0200)
pmsm-control/div8.vhdl [new file with mode: 0644]
pmsm-control/rpi_mc_simple_dc.vhdl
pmsm-control/syn.tcl

diff --git a/pmsm-control/div8.vhdl b/pmsm-control/div8.vhdl
new file mode 100644 (file)
index 0000000..f243183
--- /dev/null
@@ -0,0 +1,36 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.util.all;
+
+entity div8 is
+
+port (
+       clk_in: in std_logic;
+       clk_out: out std_logic
+);
+end div8;
+
+
+architecture behavioral of div8 is
+       signal count : std_logic_vector (2 downto 0);
+begin
+       
+       
+       divider : process 
+       begin
+               wait until (clk_in'event and clk_in='1');
+               if (count="111") then
+                       count<="000";
+               else
+                       count <= std_logic_vector(unsigned(count) + 1);
+               end if;
+                       clk_out <= count(2);
+    end process divider;
+
+       
+               
+end behavioral;
+
index 3d188e0..1591fba 100644 (file)
@@ -133,6 +133,14 @@ architecture behavioral of rpi_mc_simple_dc is
        );
        end component;
        
+       component div8 is
+       port (
+               --reset: in std_logic;
+               clk_in: in std_logic;
+               clk_out: out std_logic
+       );
+       end component;
+       
        
        type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
        signal state : state_type;
@@ -166,6 +174,8 @@ architecture behavioral of rpi_mc_simple_dc is
        
        signal income_data_valid: std_logic;
        
+       signal clk_3M1: std_logic;
+       
        
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
@@ -222,6 +232,14 @@ begin
        end generate;
        
        
+       div8_map: div8 
+       port map(
+               --reset => income_data_valid,
+               clk_in => gpio_clk,
+               clk_out => clk_3M1
+       );
+
+       
        
        --   pll: pll50to200
        --     port map (
@@ -328,7 +346,7 @@ begin
                variable reset_re: std_logic:='0';
                variable reset_count: integer:=0;
        begin
-               wait until (gpio_clk'event and gpio_clk='1');
+               wait until (clk_3M1'event and clk_3M1='1');
                
                --reset rising edge detection
                adc_rst_old(0)<=adc_reset;
index 7fb9702..33b7f81 100644 (file)
@@ -8,6 +8,7 @@ add_file util.vhdl
 add_file qcounter.vhdl
 add_file dff.vhdl
 add_file mcpwm.vhdl
+add_file div8.vhdl
 
 # top-level
 add_file rpi_mc_simple_dc.vhdl