Unused lines removed.

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index 7d6cc92a3cd9375a479ab02512fd325669bc1b45..c4471187a39ad2605bc816238048cdeac9684b45 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -118,10 +118,7 @@ architecture behavioral of rpi_mc_simple_dc is
        signal spi_clk: std_logic;
        signal gpio_clk: std_logic;
        signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
        signal spi_clk: std_logic;
        signal gpio_clk: std_logic;
        signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi

-       signal spi_ctrl : std_logic_vector (96 downto 0); --ctrl reg for spi, in use when thers no falling edge of CS

        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru

-       --signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
-       --signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin

        signal ce0_old: std_logic_vector(1 downto 0);
        
        --  attribute syn_noprune of gpio2 : signal is true;
        signal ce0_old: std_logic_vector(1 downto 0);
        
        --  attribute syn_noprune of gpio2 : signal is true;


@@ -204,17 +201,6 @@ begin
        pwm(3) <= '0';
 
        
        pwm(3) <= '0';
 
        

---     process(gpio_clk)
---     begin
---             if gpio_clk= '1' and gpio_clk'event then
---                     spiclk_old_lvl<=spi_clk;
---             end if;
---     end process;
---     spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
---     spi_clk_fall <= (not spi_clk) and spiclk_old_lvl; 
- 
-  
---     process(spi_clk_fall,spi_clk_rise)

        process
        begin
                --position is obtained on rising edge -> we should write it on falling edge
        process
        begin
                --position is obtained on rising edge -> we should write it on falling edge


@@ -231,7 +217,6 @@ begin
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                                dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                                dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;

-                               --spi_ctrl(96 downto 0) <= spi_ctrl(95 downto 0) & spi_ctrl(96); --shift ctrl reg 

                                end if;
                elsif (spiclk_old="10" ) then --falling edge, faze zapisu
                        if (gpio7 = '0') then
                                end if;
                elsif (spiclk_old="10" ) then --falling edge, faze zapisu
                        if (gpio7 = '0') then


@@ -244,10 +229,7 @@ begin
                if ((ce0_old = "10") ) then 
                        dat_reg(95 downto 64) <= position(31 downto 0); --pozice
                        dat_reg(63 downto 0) <= (others => '1'); --zbytek zatim nuly
                if ((ce0_old = "10") ) then 
                        dat_reg(95 downto 64) <= position(31 downto 0); --pozice
                        dat_reg(63 downto 0) <= (others => '1'); --zbytek zatim nuly

-                       --spiclk_old <= "00"; --bez tohoto prirazeni chodila v ~12% chybna data
-                       --no falling edge conroll
-                       --spi_ctrl(96 downto 1) <=(others=>'0');
-                       --spi_ctrl(0)<='1';
+

                end if;
        end process;
        
                end if;
        end process;