ADC basic state machine. Not complete.

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index e910bf8b1630cc3d2f0014ba4a8b4418700542be..35de1b8ecaecd4c4fa5d0b781b82adf6f904a44b 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -60,9 +60,9 @@ port (
        power_stat: in std_logic;
        -- ADC for current
        adc_miso: in std_logic;
-       adc_mosi: in std_logic;
-       adc_sclk: in std_logic;
-       adc_scs: in std_logic;
+       adc_mosi: out std_logic;
+       adc_sclk: out std_logic;
+       adc_scs: out std_logic;
        -- Extarnal SPI
        ext_miso: in std_logic; --master in slave out
        ext_mosi: in std_logic; --master out slave in
@@ -113,6 +113,10 @@ architecture behavioral of rpi_mc_simple_dc is
        );
        end component;
 
+       type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
+       signal state : state_type;
+       signal adc_data: std_logic_vector(11 downto 0); --ADC income data
+       
        signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
        signal pwm_in, pwm_dir_in: std_logic;
        signal gpio_clk: std_logic;
@@ -120,6 +124,8 @@ architecture behavioral of rpi_mc_simple_dc is
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
        signal ce0_old: std_logic_vector(1 downto 0);
        
+       
+       
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
@@ -171,7 +177,7 @@ begin
                stat(1) and stat(2) and stat(3) and
                hal_in(1) and hal_in(2) and hal_in(3) and
                irc_i and power_stat and 
-               adc_miso and adc_mosi and adc_sclk and adc_scs and
+               adc_miso and 
                rs485_rxd and
                can_rx and can_tx and
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
@@ -228,6 +234,118 @@ begin
                end if;
        end process;
        
+       process 
+       begin
+               wait until (gpio_clk'event and gpio_clk='1');
+               case state is
+                       when f1=>
+                               adc_sclk<='0'; --clk
+                               adc_scs<='0'; --active-high SS
+                               adc_mosi<='1'; --start bit
+                               state<=r1; --next state
+                       when r1=>       --rising edge
+                               adc_sclk<='1';
+                               adc_data(5)<=adc_miso;
+                               state<=f2;
+                       when f2=> --2nd falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='0'; --A2 address
+                               state<=r2;
+                       when r2=> --rising edge
+                               adc_sclk<='1';
+                               adc_data(4)<=adc_miso;
+                               state<=f3;
+                       when f3=> --3rd falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='0'; --A1 address
+                               state<=r3;
+                       when r3=> --rising edge
+                               adc_sclk<='1';
+                               adc_data(3)<=adc_miso;
+                               state<=f4;      
+                       when f4=> --4th falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='1'; --A0 address
+                               state<=r4;
+                       when r4=> --rising edge
+                               adc_sclk<='1';
+                               adc_data(2)<=adc_miso;
+                               state<=f5;      
+                       when f5=> --5th falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='0'; --MODE (LOW -12bit)
+                               state<=r5;
+                       when r5=> --rising edge
+                               adc_sclk<='1';
+                               adc_data(1)<=adc_miso;
+                               state<=f6;      
+                       when f6=> --6th falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
+                               state<=r6;
+                       when r6=> --rising edge
+                               adc_sclk<='1';
+                               adc_data(0)<=adc_miso;
+                               state<=f7;              
+                       when f7=> -- 7th falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
+                               state<=r7;
+                       when r7=> --rising edge, data ready
+                               adc_sclk<='1';
+                               state<=f8;      
+                       when f8=> --8th falling edge
+                               adc_sclk<='0';
+                               adc_mosi<='0'; --PD0
+                               state<=r8;
+                       when r8=> --rising edge
+                               adc_sclk<='1';
+                               state<=f9;
+                       when f9=> --busy state between conversion, 9th falling edge
+                               adc_sclk<='0';
+                               state<=r9;
+                       when r9=>  --10th rising edge
+                               adc_sclk<='1';
+                               adc_data(11)<=adc_miso;
+                               state<=f10;
+                       when f10=>
+                               adc_sclk<='0';
+                               state<=r10;
+                       when r10=>  --11th rising edge
+                               adc_sclk<='1';
+                               adc_data(10)<=adc_miso;
+                               state<=f11;
+                       when f11=>
+                               adc_sclk<='0';
+                               state<=r11;
+                       when r11=>  --12th rising edge
+                               adc_sclk<='1';
+                               adc_data(9)<=adc_miso;
+                               state<=f12;
+                       when f12=>
+                               adc_sclk<='0';
+                               state<=r12;
+                       when r12=>  --13th rising edge
+                               adc_sclk<='1';
+                               adc_data(8)<=adc_miso;
+                               state<=f13;
+                       when f13=>
+                               adc_sclk<='0';
+                               state<=r13;
+                       when r13=>  --14th rising edge
+                               adc_sclk<='1';
+                               adc_data(7)<=adc_miso;
+                               state<=f14;
+                       when f14=>
+                               adc_sclk<='0';
+                               state<=r14;
+                       when r14=> --15th rising edge
+                               adc_data(6)<=adc_miso;
+                               state<=f1;
+               end case;
+       end process;
+                       
+       
                
 end behavioral;