Use of external, not synchronized signal event as
the trigger condition results in creation of additional
clock domain which can result in all kinds of hazard
conditions when used to manipulate with else synchronous
design state.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
signal income_data_valid: std_logic;
signal clk_4M17: std_logic;
signal income_data_valid: std_logic;
signal clk_4M17: std_logic;
+
+ -- irc signals processing
+ signal irc_i_prev: std_logic;
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
- wait until (irc_i'event and irc_i='1');
- index_position(11 downto 0)<=position(11 downto 0);
+ wait until (gpio_clk'event and gpio_clk='1');
+ if irc_i_prev = '0' and irc_i = '1' then
+ index_position(11 downto 0)<=position(11 downto 0);
+ end if;
+ irc_i_prev<=irc_i;