Change IRC recognition logic synchronous with main design clock.
authorPavel Pisa <ppisa@pikron.com>
Fri, 1 May 2015 15:48:28 +0000 (17:48 +0200)
committerPavel Pisa <ppisa@pikron.com>
Fri, 1 May 2015 15:48:28 +0000 (17:48 +0200)
Use of external, not synchronized signal event as
the trigger condition results in creation of additional
clock domain which can result in all kinds of hazard
conditions when used to manipulate with else synchronous
design state.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
pmsm-control/rpi_pmsm_control.vhdl

index c3f8416..f8e8bd5 100644 (file)
@@ -193,8 +193,9 @@ architecture behavioral of rpi_pmsm_control is
        signal income_data_valid: std_logic;
        
        signal clk_4M17: std_logic;
-       
-       
+
+       -- irc signals processing
+       signal irc_i_prev: std_logic;
        
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
@@ -316,8 +317,11 @@ begin
                
        process
        begin
-               wait until (irc_i'event and irc_i='1');
-               index_position(11 downto 0)<=position(11 downto 0);
+               wait until (gpio_clk'event and gpio_clk='1');
+               if irc_i_prev = '0' and irc_i = '1' then
+                       index_position(11 downto 0)<=position(11 downto 0);
+               end if;
+               irc_i_prev<=irc_i;
        end process;
        
        process