signal clk_3M1: std_logic;
+
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
-- attribute syn_keep of gpio2 : signal is true;
match => pwm_match(i),
count => pwm_count,
-- outputs
- out_p => open,--pwm(i), --positive signal
- out_n => open--shdn(i) --reverse signal is in shutdown mode
+ out_p => pwm(i), --positive signal
+ out_n => shdn(i) --reverse signal is in shutdown mode
);
end generate;
rs485_dir <= '0';
- shdn(1) <= '1';
- shdn(2) <= '1';
- shdn(3) <= '1';
+ --shdn(1) <= '0';
+ --shdn(2) <= '1';
+ --shdn(3) <= '0';
- pwm(1) <= '0';
- pwm(2) <= '0';
- pwm(3) <= '0';
+ --pwm(1) <= '0';
+ --pwm(2) <= '0';
+ --pwm(3) <= '0';
process
begin
income_data_valid<='0';
dat_reg(95 downto 64) <= position(31 downto 0); --pozice
dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
- dat_reg(60 downto 36) <= (others => '1'); --let the rest fill with ones
+ dat_reg(60 downto 58) <= pwm_en_p(1 to 3); --enable positive
+ dat_reg(57 downto 55) <= pwm_en_n(1 to 3); --shutdown
+ dat_reg(54 downto 49) <= pwm_match(1)(10 downto 5); --6 MSb of PWM1
+ dat_reg(48 downto 42) <= pwm_match(2)(10 downto 4); --7 MSb of PWM2
+ dat_reg(41 downto 36) <= pwm_match(3)(10 downto 5); --6 MSb of PWM3
dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
adc_reset<='0'; --remove reset flag, and wait on its rising edge
elsif (ce0_old = "01") then --rising edge of SS, we should read the data
pwm_en_n(1 to 3)<=dat_reg(91 downto 89);
--11 bit pwm TODO: make it generic
pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(34 downto 24);
- pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(22 downto 12);
+ pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(23 downto 13);
+ -- 12 + 11 Unused
pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(10 downto 0);
income_data_valid<='1';
end if;