testovani nahravani vhdl. Zmena logicke hodnoty na pinu 7 na HIGH

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index 3eac4f6e4d2395819b8541f19b6f49972028b17a..1198651a4f0f6abf0cd7d2a0d2e11cde53cacb98 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -65,7 +65,7 @@ entity rpi_mc_simple_dc is
     adc_scs: in std_logic;
     -- Extarnal SPI
     ext_miso: in std_logic; --master in slave out
-    ext_mosi: in std_logic;
+    ext_mosi: in std_logic; --master out slave in
     ext_sclk: in std_logic;
     ext_scs0: in std_logic;
     ext_scs1: in std_logic;
@@ -144,7 +144,7 @@ begin
   gpio23 <= irc_a;
   gpio24 <= irc_a;
 
-  gpio7 <= irc_b;
+  gpio7 <= '1';
   gpio8 <= irc_b;
 
   pwm_in <= gpio18;