Added synchronous detection o divided clk signal to adc_reader component.

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index 8f2f2c5656ab9b2ab8717a355401d492a86aba79..219841c2c93a038aa1e6cbd37bcd311e4fe53db9 100644 (file)
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -21,13 +21,16 @@ use work.util.all;
 
 entity adc_reader is
 port (
 
 entity adc_reader is
 port (

-       clk: in std_logic;                                      --input clk
-       adc_reset: in std_logic;
+       clk: in std_logic;                                      --synchronous master clk
+       divided_clk : in std_logic;                             --divided clk - value suitable to sourcing voltage
+       adc_reset: in std_logic;                                --synchronous reset on rising edge
+       

        adc_miso: in std_logic;                                 --spi master in slave out
        adc_miso: in std_logic;                                 --spi master in slave out

-       adc_channels: out std_logic_vector (71 downto 0);       --consistent data of 3 channels

        adc_sclk: out std_logic;                                --spi clk
        adc_scs: out std_logic;                                 --spi slave select
        adc_mosi: out std_logic;                                --spi master out slave in
        adc_sclk: out std_logic;                                --spi clk
        adc_scs: out std_logic;                                 --spi slave select
        adc_mosi: out std_logic;                                --spi master out slave in

+       
+       adc_channels: out std_logic_vector (71 downto 0);       --consistent data of 3 channels

        measur_count: out std_logic_vector(8 downto 0)          --number of accumulated measurments
        
 );
        measur_count: out std_logic_vector(8 downto 0)          --number of accumulated measurments
        
 );


@@ -43,12 +46,13 @@ architecture behavioral of adc_reader is
        type channel_type is (ch0, ch1, ch2);
        
        signal adc_data: std_logic_vector(11 downto 0); 
        type channel_type is (ch0, ch1, ch2);
        
        signal adc_data: std_logic_vector(11 downto 0); 

-       signal adc_rst_old : std_logic_vector(1 downto 0);
+       signal adc_rst_prev : std_logic;

        signal adc_address: std_logic_vector(2 downto 0);
        signal cumul_data: std_logic_vector(71 downto 0);       --unconsistent data, containing different amounts of measurments
        signal prepared_data: std_logic_vector(71 downto 0);    --consistent data, waiting for clk sync to propagate to output
        signal m_count_sig: std_logic_vector(8 downto 0);       --measurments count waiting for clk to propagate to output
        signal first_pass: std_logic;
        signal adc_address: std_logic_vector(2 downto 0);
        signal cumul_data: std_logic_vector(71 downto 0);       --unconsistent data, containing different amounts of measurments
        signal prepared_data: std_logic_vector(71 downto 0);    --consistent data, waiting for clk sync to propagate to output
        signal m_count_sig: std_logic_vector(8 downto 0);       --measurments count waiting for clk to propagate to output
        signal first_pass: std_logic;

+       signal div_clk_prev: std_logic;

 begin
        
        
 begin
        
        


@@ -60,13 +64,15 @@ begin
                wait until (clk'event and clk='1');
                
                --rising edge detection of reset signal
                wait until (clk'event and clk='1');
                
                --rising edge detection of reset signal

-               adc_rst_old(0)<=adc_reset;
-               adc_rst_old(1)<=adc_rst_old(0);
-               
-               if (adc_rst_old="01") then
+               adc_rst_prev<=adc_reset;
+               if (adc_rst_prev='0') and (adc_reset='1') then

                        reset_re:='1';
                end if;
                
                        reset_re:='1';
                end if;
                

+               --rising edge detection of divided clk signal
+               div_clk_prev<=divided_clk;
+               if (divided_clk='1') and (div_clk_prev='0') then
+               

                case state is
                        when reset=>
                                reset_re:='0';                  --clear reset flag
                case state is
                        when reset=>
                                reset_re:='0';                  --clear reset flag


@@ -233,6 +239,9 @@ begin
                                        state<=f1;
                                end if;
                end case;
                                        state<=f1;
                                end if;
                end case;

+               
+               end if;
+               

        end process;
                        
        
        end process;
                        
        

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 2127d2e93554f937e4c39db52f6a437f94a7aa38..413f11c297fff1499e8df1aa55c2e6a2d6789ffc 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -154,6 +154,7 @@ architecture behavioral of rpi_pmsm_control is
        component adc_reader is
        port (
                clk: in std_logic;                                      --input clk
        component adc_reader is
        port (
                clk: in std_logic;                                      --input clk

+               divided_clk : in std_logic;                             --divided clk - value suitable to sourcing voltage

                adc_reset: in std_logic;
                adc_miso: in std_logic;                                 --spi master in slave out
                adc_channels: out std_logic_vector (35 downto 0);       --consistent data of 3 channels
                adc_reset: in std_logic;
                adc_miso: in std_logic;                                 --spi master in slave out
                adc_channels: out std_logic_vector (35 downto 0);       --consistent data of 3 channels


@@ -290,7 +291,8 @@ begin
        --        while we use +3.3V Vcc     
        adc_reader_map: adc_reader 
        port map(
        --        while we use +3.3V Vcc     
        adc_reader_map: adc_reader 
        port map(

-               clk =>clk_4M17,
+               clk => gpio_clk,
+               divided_clk => clk_4M17,

                adc_reset => adc_reset,
                adc_miso => adc_miso,
                adc_channels => adc_channels,
                adc_reset => adc_reset,
                adc_miso => adc_miso,
                adc_channels => adc_channels,