Include SDC Synopsys Design Constraints file to the design file lists.

This file allows fine definition of clocks relations and parameters.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/pmsm-control/syn.tcl b/pmsm-control/syn.tcl
index 19ab95ad2afbfaf1413efb7e7bff395d3d853d82..b444b9dac063de30147dfd660a9b2f81ad430903 100644 (file)
--- a/pmsm-control/syn.tcl
+++ b/pmsm-control/syn.tcl
@@ -3,7 +3,7 @@
 project -new rpi_pmsm_control
 impl -name syn0
 
-#add_file pll50to200.vhd
+add_file pll50to200.vhd
 add_file util.vhdl
 add_file qcounter.vhdl
 add_file dff.vhdl
@@ -13,14 +13,14 @@ add_file adc_reader.vhdl
 
 # top-level
 add_file rpi_pmsm_control.vhdl
-#add_file rpi_mc_simple_dc.sdc
+add_file rpi_pmsm_control.sdc
 
 set_option -technology IGLOO
 set_option -part AGL250V5
 set_option -package VQFP100
 set_option -speed_grade std
 
-set_option -frequency 40.0
+set_option -frequency 50.0
 
 project -run
 project -save