Added UNTESTED version of spi-commands-lost detection.
authorMartin Prudek <prudemar@fel.cvut.cz>
Sun, 4 Oct 2015 14:34:59 +0000 (16:34 +0200)
committerMartin Prudek <prudemar@fel.cvut.cz>
Sun, 4 Oct 2015 14:34:59 +0000 (16:34 +0200)
pmsm-control/div128.vhdl [new file with mode: 0644]
pmsm-control/div256.vhdl [new file with mode: 0644]
pmsm-control/rpi_pmsm_control.vhdl
pmsm-control/syn.tcl

diff --git a/pmsm-control/div128.vhdl b/pmsm-control/div128.vhdl
new file mode 100644 (file)
index 0000000..b63d1dd
--- /dev/null
@@ -0,0 +1,46 @@
+-- provides frequency division by 12
+-- initialy intended to make 4.17Mhz from 50Mhz 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.util.all;
+
+entity div128 is
+
+port (
+       clk_in: in std_logic;
+       rst: in std_logic;
+       fail_safe: out std_logic
+);
+end div128;
+
+
+architecture behavioral of div128 is
+       signal count : std_logic_vector (6 downto 0);
+       signal rst_prev: std_logic;
+begin
+       
+       
+       seq : process 
+       begin
+               wait until (clk_in'event and clk_in='1');
+               rst_prev <= rst;
+               if rst='1' and rst_prev='0' then
+                       count <= "0000000";
+                       fail_safe <= '0';
+               else
+                       count <= std_logic_vector(unsigned(count) + 1);
+               end if;
+               
+               if count = "1111111" then
+                       fail_safe <= '1';
+               else 
+                       fail_safe <= '0';
+               end if;
+       end process;
+
+       
+               
+end behavioral;
+
diff --git a/pmsm-control/div256.vhdl b/pmsm-control/div256.vhdl
new file mode 100644 (file)
index 0000000..26be680
--- /dev/null
@@ -0,0 +1,32 @@
+-- provides frequency division by 256 (8 bit divider)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.util.all;
+
+entity div256 is
+
+port (
+       clk_in: in std_logic;
+       div256: out std_logic
+);
+end div256;
+
+
+architecture behavioral of div256 is
+       signal count : std_logic_vector (8 downto 0);
+begin
+       
+       div256 <= count(8);
+       
+       seq : process 
+       begin
+               wait until (clk_in'event and clk_in='1');
+               count <= std_logic_vector(unsigned(count) + 1);
+       end process;
+
+       
+               
+end behavioral;
+
index 177029f..22b9f7d 100644 (file)
@@ -181,6 +181,22 @@ architecture behavioral of rpi_pmsm_control is
        );
        end component;
        
+       --resetovatelna delicka
+       component div128 is
+       port (
+               clk_in: in std_logic;
+               rst: in std_logic;
+               fail_safe: out std_logic
+       );
+       end component;
+       
+       component div256 is
+       port (
+               clk_in: in std_logic;
+               div256: out std_logic
+       );
+       end component;
+       
        
        signal adc_channels: std_logic_vector(71 downto 0);
        signal adc_m_count: std_logic_vector(8 downto 0);
@@ -229,6 +245,11 @@ architecture behavioral of rpi_pmsm_control is
        signal irc_a_dff3: std_logic;
        signal irc_b_dff3: std_logic;
        
+       --16k3 clk signal
+       signal clk_16k3: std_logic;
+       --detekce prichazejicich prikazu po SPI
+       signal spi_command_lost: std_logic;
+       
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
@@ -306,6 +327,19 @@ begin
                q_out_o   =>clk_4M17
        );
        
+       div256_map: div256 
+       port map(
+               clk_in => clk_4M17,
+               div256 => clk_16k3
+       );
+       
+       div128_map: div128 
+       port map(
+               clk_in => clk_16k3,
+               rst => income_data_valid,
+               fail_safe => spi_command_lost
+);
+
        -- ADC needs 3.2 MHz clk when powered from +5V Vcc
        --           2.0 MHz clk when +2.7V Vcc
        -- on the input is 4.17Mhz,but this frequency is divided inside adc_reader by 2 to 2.08 Mhz,
@@ -363,9 +397,9 @@ begin
        spi_mosi <= gpio10;
        gpio9 <= spi_miso;
 
-       pwm(1) <= pwm_sig(1) and dip_sw(1);
-       pwm(2) <= pwm_sig(2) and dip_sw(2);
-       pwm(3) <= pwm_sig(3) and dip_sw(3);
+       pwm(1) <= pwm_sig(1) and dip_sw(1) and not spi_command_lost;
+       pwm(2) <= pwm_sig(2) and dip_sw(2) and not spi_command_lost;
+       pwm(3) <= pwm_sig(3) and dip_sw(3) and not spi_command_lost;
        
                
        process
index c600086..8052141 100644 (file)
@@ -11,6 +11,8 @@ add_file mcpwm.vhdl
 add_file cnt_div.vhdl
 add_file adc_reader.vhdl
 add_file dff3.vhdl
+add_file div128.vhdl
+add_file div256.vhdl
 
 # top-level
 add_file rpi_pmsm_control.vhdl