GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for...
authorMartin Prudek <prudemar@fel.cvut.cz>
Sat, 11 Apr 2015 09:14:13 +0000 (11:14 +0200)
committerMartin Prudek <prudemar@fel.cvut.cz>
Sat, 11 Apr 2015 09:14:13 +0000 (11:14 +0200)
commitc9725d8efd262634d0ea8c5471d5b9e1b77a59cb
tree23ef681de02a6ee7fd12f435e3511ff3a0f643ce
parentb060c36616ed147804417bfbb1199b4f7d5cfa3d
GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for ADC lower then 3.2Mhz, freqency divider(divides by 8) have been added.
pmsm-control/div8.vhdl [new file with mode: 0644]
pmsm-control/rpi_mc_simple_dc.vhdl
pmsm-control/syn.tcl