Change IRC recognition logic synchronous with main design clock.
authorPavel Pisa <ppisa@pikron.com>
Fri, 1 May 2015 15:48:28 +0000 (17:48 +0200)
committerPavel Pisa <ppisa@pikron.com>
Fri, 1 May 2015 15:48:28 +0000 (17:48 +0200)
commit5e9d551775408b98dd40058d4ba5ae0603cb3752
tree97101328b155b3b79297995d250ebe6f30d5690e
parent34de8485a125ab8edae50d0f1406462a82b56391
Change IRC recognition logic synchronous with main design clock.

Use of external, not synchronized signal event as
the trigger condition results in creation of additional
clock domain which can result in all kinds of hazard
conditions when used to manipulate with else synchronous
design state.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
pmsm-control/rpi_pmsm_control.vhdl