X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/ec04aea839eaf69fd788d8fbeb606f685df1d157..ee6653b06cc0c19947e2ad3cd675a8e4121c00c6:/pmsm-control/rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index beb4b9c..13ffb97 100644
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -144,10 +144,17 @@ architecture behavioral of rpi_pmsm_control is
 	end component;
 	
 	--frequency division by 12
-	component divider is
-	port (
-		clk_in: in std_logic;
-		div12: out std_logic
+	component cnt_div is
+	generic (
+		cnt_width_g : natural := 4
+	);
+	port
+	(
+		clk_i     : in std_logic;				--clk to divide
+		en_i      : in std_logic;				--enable bit?
+		reset_i   : in std_logic;				--asynch. reset
+		ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+		q_out_o   : out std_logic				--generates puls when counter underflows
 	);
 	end component;
 	
@@ -278,11 +285,13 @@ begin
 	end generate;
 	
 	
-	div12_map: divider
+	div12_map: cnt_div
 	port map(
-		--reset => income_data_valid,
-		clk_in => gpio_clk,
-		div12 => clk_4M17
+		clk_i  => gpio_clk,
+		en_i   =>'1',
+		reset_i   =>'0',
+		ratio_i   =>"1101", --POZN.: counter detekuje cnt<=1
+		q_out_o   =>clk_4M17
 	);
 	
 	-- ADC needs 3.2 MHz clk when powered from +5V Vcc