X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/ec04aea839eaf69fd788d8fbeb606f685df1d157..1c8eb36a8a3c7e271cc07ee6d25120c950fb0160:/pmsm-control/rpi_pmsm_control.vhdl?ds=sidebyside

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index beb4b9c..22b9f7d 100644
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -144,10 +144,17 @@ architecture behavioral of rpi_pmsm_control is
 	end component;
 	
 	--frequency division by 12
-	component divider is
-	port (
-		clk_in: in std_logic;
-		div12: out std_logic
+	component cnt_div is
+	generic (
+		cnt_width_g : natural := 4
+	);
+	port
+	(
+		clk_i     : in std_logic;				--clk to divide
+		en_i      : in std_logic;				--enable bit?
+		reset_i   : in std_logic;				--asynch. reset
+		ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+		q_out_o   : out std_logic				--generates puls when counter underflows
 	);
 	end component;
 	
@@ -166,6 +173,30 @@ architecture behavioral of rpi_pmsm_control is
 	);
 	end component;
 	
+	component dff3 is
+	port(
+		clk_i   : in std_logic;
+		d_i     : in std_logic;
+		q_o     : out std_logic
+	);
+	end component;
+	
+	--resetovatelna delicka
+	component div128 is
+	port (
+		clk_in: in std_logic;
+		rst: in std_logic;
+		fail_safe: out std_logic
+	);
+	end component;
+	
+	component div256 is
+	port (
+		clk_in: in std_logic;
+		div256: out std_logic
+	);
+	end component;
+	
 	
 	signal adc_channels: std_logic_vector(71 downto 0);
 	signal adc_m_count: std_logic_vector(8 downto 0);
@@ -210,6 +241,15 @@ architecture behavioral of rpi_pmsm_control is
 	-- irc signals processing
 	signal irc_i_prev: std_logic;
 	
+	--filetered irc signals
+	signal irc_a_dff3: std_logic;
+	signal irc_b_dff3: std_logic;
+	
+	--16k3 clk signal
+	signal clk_16k3: std_logic;
+	--detekce prichazejicich prikazu po SPI
+	signal spi_command_lost: std_logic;
+	
 	--  attribute syn_noprune of gpio2 : signal is true;
 	--  attribute syn_preserve of gpio2 : signal is true;
 	--  attribute syn_keep of gpio2 : signal is true;
@@ -243,8 +283,8 @@ begin
 	port map (
 		clock => gpio_clk,
 		reset => '0',
-		a0 => irc_a,
-		b0 => irc_b,
+		a0 => irc_a_dff3,
+		b0 => irc_b_dff3,
 		qcount => position,
 		a_rise => open,
 		a_fall => open,
@@ -278,13 +318,28 @@ begin
 	end generate;
 	
 	
-	div12_map: divider
+	div12_map: cnt_div
+	port map(
+		clk_i  => gpio_clk,
+		en_i   =>'1',
+		reset_i   =>'0',
+		ratio_i   =>"1101", --POZN.: counter detekuje cnt<=1
+		q_out_o   =>clk_4M17
+	);
+	
+	div256_map: div256 
 	port map(
-		--reset => income_data_valid,
-		clk_in => gpio_clk,
-		div12 => clk_4M17
+		clk_in => clk_4M17,
+		div256 => clk_16k3
 	);
 	
+	div128_map: div128 
+	port map(
+		clk_in => clk_16k3,
+		rst => income_data_valid,
+		fail_safe => spi_command_lost
+);
+
 	-- ADC needs 3.2 MHz clk when powered from +5V Vcc
 	--	     2.0 MHz clk when +2.7V Vcc
 	-- on the input is 4.17Mhz,but this frequency is divided inside adc_reader by 2 to 2.08 Mhz,
@@ -302,6 +357,20 @@ begin
 		measur_count => adc_m_count
 		
 	);
+	
+	dff3_a: dff3
+	port map(	
+		clk_i => gpio_clk,
+		d_i   => irc_a,
+		q_o   => irc_a_dff3 
+	);
+	
+	dff3_b: dff3
+	port map(	
+		clk_i => gpio_clk,
+		d_i   => irc_b,
+		q_o   => irc_b_dff3 
+	);
 
 	dummy_unused <= gpio2 and gpio3 and
 		gpio5 and gpio6 and
@@ -328,9 +397,9 @@ begin
 	spi_mosi <= gpio10;
 	gpio9 <= spi_miso;
 
-	pwm(1) <= pwm_sig(1) and dip_sw(1);
-	pwm(2) <= pwm_sig(2) and dip_sw(2);
-	pwm(3) <= pwm_sig(3) and dip_sw(3);
+	pwm(1) <= pwm_sig(1) and dip_sw(1) and not spi_command_lost;
+	pwm(2) <= pwm_sig(2) and dip_sw(2) and not spi_command_lost;
+	pwm(3) <= pwm_sig(3) and dip_sw(3) and not spi_command_lost;
 	
 		
 	process