X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/e9eadbd980bbd3a738745368c2e8acbe189b79b4..c4cdcbe5bfaecb9024e4fe41be29a4541653b8ef:/pmsm-control/adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index c792525..cda8cc7 100644
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -10,10 +10,11 @@ port (
 	clk: in std_logic;					--input clk
 	adc_reset: in std_logic;
 	adc_miso: in std_logic;					--spi master in slave out
-	adc_channels: out std_logic_vector (35 downto 0);	--consistent data of 3 channels
+	adc_channels: out std_logic_vector (71 downto 0);	--consistent data of 3 channels
 	adc_sclk: out std_logic; 				--spi clk
 	adc_scs: out std_logic;					--spi slave select
-	adc_mosi: out std_logic					--spi master out slave in
+	adc_mosi: out std_logic;				--spi master out slave in
+	measur_count: out std_logic_vector(8 downto 0)		--number of accumulated measurments
 	
 );
 end adc_reader;
@@ -30,11 +31,14 @@ architecture behavioral of adc_reader is
 	signal adc_data: std_logic_vector(11 downto 0); 
 	signal adc_rst_old : std_logic_vector(1 downto 0);
 	signal adc_address: std_logic_vector(2 downto 0);
+	signal cumul_data: std_logic_vector(71 downto 0);	--unconsistent data, containing different amounts of measurments
+	signal prepared_data: std_logic_vector(71 downto 0);	--consistent data, waiting for clk sync to propagate to output
+	signal m_count_sig: std_logic_vector(8 downto 0);	--measurments count waiting for clk to propagate to output
+	signal first_pass: std_logic;
 begin
 	
 	
 	process 
-		variable data_ready : std_logic;
 		variable channel: channel_type;
 		variable reset_re: std_logic:='0';
 		variable reset_count: std_logic_vector (3 downto 0);
@@ -54,8 +58,14 @@ begin
 				reset_re:='0'; 			--clear reset flag
 				adc_scs<='1'; 			--active-low SS
 				adc_sclk<='0'; 			--lower clock
-				data_ready:='0'; 		--mark data as unprepared
+				first_pass<='1'; 		--mark data as unprepared
 				channel:=ch0;			--prepare channel0
+				adc_data<=(others=>'0');	--null working data
+				cumul_data<=(others=>'0');	--null working data
+				prepared_data<=(others=>'0');	--null the output
+				adc_channels<=(others=>'0');	--null the output
+				measur_count<=(others=>'0');	--null the count
+				m_count_sig<=(others=>'0');	--null the count
 				adc_address<="001";		--set its address
 				reset_count:="0000";
 				state<=rst_wait;
@@ -121,30 +131,40 @@ begin
 				state<=r7;
 			when r7=> --7th rising edge, data ready
 				adc_sclk<='1';
-				if (data_ready='1') then
+				if (first_pass='0') then
+					--add the current current to sum and shift the register
+					cumul_data(71 downto 0)<=
+						std_logic_vector(unsigned(cumul_data(47 downto 24))
+							+unsigned(adc_data(11 downto 0)))
+						& cumul_data(23 downto 0)
+						& cumul_data(71 downto 48);
+				end if;
+				state<=f8;
+			when f8=> --8th falling edge
+				adc_sclk<='0';
+				adc_mosi<='0'; --PD0
+				if (first_pass='0') then
 					case channel is
 						when ch0=>
-							adc_channels(35 downto 24)<=adc_data(11 downto 0);
 							adc_address<="101";	--ch1 address
-							channel:=ch1;
+							channel:=ch1;		--next channel code
 						when ch1=>
-							adc_channels(23 downto 12)<=adc_data(11 downto 0);
 							adc_address<="010";	--ch2 address
-							channel:=ch2;
+							channel:=ch2;		--next channel code
 						when ch2=>
-							adc_channels(11 downto 0)<=adc_data(11 downto 0);
+							--data order schould be: ch2 downto ch0 downto ch1
+							prepared_data(71 downto 0)<=cumul_data(71 downto 0);
+							m_count_sig<=std_logic_vector(unsigned(m_count_sig)+1);
 							adc_address<="001";	--ch0 address
-							channel:=ch0;
+							channel:=ch0;		--next channel code
 					end case;
 				end if;
-				data_ready:='1';
-				state<=f8;	
-			when f8=> --8th falling edge
-				adc_sclk<='0';
-				adc_mosi<='0'; --PD0
 				state<=r8;
-			when r8=> --8th rising edge (adc gets PD0)
+			when r8=> --8th rising edge (adc gets PD0), we propagate our results to output
 				adc_sclk<='1';
+				adc_channels <= prepared_data;		--data
+				measur_count <= m_count_sig;		--count of measurments
+				first_pass<='0';			--data in next cycle are usable
 				state<=f9;
 			when f9=> --9th falling edge busy state between conversion (we write nothing)
 				adc_sclk<='0';
@@ -155,7 +175,7 @@ begin
 			when f10=> --10th falling edge
 				adc_sclk<='0';
 				state<=r10;
-			when r10=>  --10th rising edge (we read 1. bit of conversion)
+			when r10=>  --10th rising edge (we read 1. bit of new conversion)
 				adc_sclk<='1';
 				adc_data(11)<=adc_miso;
 				state<=f11;