X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/d8beff6a4eec064294706dadba09ac1495aef235..2b61616a5aa4846669ae9c83f5f90a71d6ef26ed:/pmsm-control/adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index 14b2faa..8f2f2c5 100644
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -1,4 +1,18 @@
-
+--
+-- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board *
+-- SPI connected multichannel current ADC read and averaging
+--
+-- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
+-- Czech Technical University in Prague
+--
+-- Project supervision and original project idea
+-- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
+--
+-- Related RPi-MI-1 hardware is designed by Petr Porazil,
+-- PiKRON Ltd  <http://www.pikron.com>
+--
+-- license: GNU LGPL and GPLv3+
+--
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -34,11 +48,11 @@ architecture behavioral of adc_reader is
 	signal cumul_data: std_logic_vector(71 downto 0);	--unconsistent data, containing different amounts of measurments
 	signal prepared_data: std_logic_vector(71 downto 0);	--consistent data, waiting for clk sync to propagate to output
 	signal m_count_sig: std_logic_vector(8 downto 0);	--measurments count waiting for clk to propagate to output
+	signal first_pass: std_logic;
 begin
 	
 	
 	process 
-		variable data_ready : std_logic;
 		variable channel: channel_type;
 		variable reset_re: std_logic:='0';
 		variable reset_count: std_logic_vector (3 downto 0);
@@ -58,7 +72,7 @@ begin
 				reset_re:='0'; 			--clear reset flag
 				adc_scs<='1'; 			--active-low SS
 				adc_sclk<='0'; 			--lower clock
-				data_ready:='0'; 		--mark data as unprepared
+				first_pass<='1'; 		--mark data as unprepared
 				channel:=ch0;			--prepare channel0
 				adc_data<=(others=>'0');	--null working data
 				cumul_data<=(others=>'0');	--null working data
@@ -131,7 +145,7 @@ begin
 				state<=r7;
 			when r7=> --7th rising edge, data ready
 				adc_sclk<='1';
-				if (data_ready='1') then
+				if (first_pass='0') then
 					--add the current current to sum and shift the register
 					cumul_data(71 downto 0)<=
 						std_logic_vector(unsigned(cumul_data(47 downto 24))
@@ -143,7 +157,7 @@ begin
 			when f8=> --8th falling edge
 				adc_sclk<='0';
 				adc_mosi<='0'; --PD0
-				if (data_ready='1') then
+				if (first_pass='0') then
 					case channel is
 						when ch0=>
 							adc_address<="101";	--ch1 address
@@ -152,18 +166,19 @@ begin
 							adc_address<="010";	--ch2 address
 							channel:=ch2;		--next channel code
 						when ch2=>
+							--data order schould be: ch2 downto ch0 downto ch1
 							prepared_data(71 downto 0)<=cumul_data(71 downto 0);
 							m_count_sig<=std_logic_vector(unsigned(m_count_sig)+1);
 							adc_address<="001";	--ch0 address
 							channel:=ch0;		--next channel code
 					end case;
 				end if;
-				data_ready:='1';
 				state<=r8;
 			when r8=> --8th rising edge (adc gets PD0), we propagate our results to output
 				adc_sclk<='1';
 				adc_channels <= prepared_data;		--data
 				measur_count <= m_count_sig;		--count of measurments
+				first_pass<='0';			--data in next cycle are usable
 				state<=f9;
 			when f9=> --9th falling edge busy state between conversion (we write nothing)
 				adc_sclk<='0';