X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/c4cdcbe5bfaecb9024e4fe41be29a4541653b8ef..24df44d1c49bcb0f29f43f577ef3d245bced9e28:/pmsm-control/rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 45ea914..c3f8416 100644
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -15,7 +15,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 
-entity rpi_mc_simple_dc is
+entity rpi_pmsm_control is
 generic(
 	pwm_width : natural:=11
 	);
@@ -85,21 +85,22 @@ port (
 	-- Unused terminal to keep design tools silent
 	dummy_unused : out std_logic
 );
-end rpi_mc_simple_dc;
+end rpi_pmsm_control;
 
 
-architecture behavioral of rpi_mc_simple_dc is
+architecture behavioral of rpi_pmsm_control is
 	attribute syn_noprune :boolean;
 	attribute syn_preserve :boolean;
 	attribute syn_keep :boolean;
 	attribute syn_hier :boolean;
+
 	-- Actel lib
-	-- component pll50to200
-	--   port (
-	--     powerdown, clka: in std_logic;
-	--     lock, gla: out std_logic
-	--   );
-	-- end component;
+	component pll50to200
+		port (
+			powerdown, clka: in std_logic;
+			lock, gla: out std_logic
+		);
+	end component;
 	
 	component CLKINT
 		port (A: in std_logic; Y: out std_logic);
@@ -133,11 +134,11 @@ architecture behavioral of rpi_mc_simple_dc is
 	);
 	end component;
 	
-	component div8 is
+	--frequency division by 12
+	component divider is
 	port (
-		--reset: in std_logic;
 		clk_in: in std_logic;
-		clk_out: out std_logic
+		div12: out std_logic
 	);
 	end component;
 	
@@ -159,10 +160,18 @@ architecture behavioral of rpi_mc_simple_dc is
 	signal adc_reset : std_logic;
 	signal adc_channels: std_logic_vector(71 downto 0);
 	signal adc_m_count: std_logic_vector(8 downto 0);
-	
+
+	--clock signals for logic and master fail monitoring
+	signal gpio_clk: std_logic;
+	signal pll_clkin, pll_clkout, pll_lock: std_logic;
+	signal clkmon_dly1, clkmon_dly2: std_logic;
+	signal clkmon_fail, clkmon_fail_next: std_logic;
+	signal clkmon_wdg: integer range 0 to 6;
+	signal reset_sync, reset_async: std_logic;
+	signal failsafe, next_failsafe: std_logic;
+
 	signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
 	--signal pwm_in, pwm_dir_in: std_logic;
-	signal gpio_clk: std_logic;
 	signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
 	signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
 	signal index_position: std_logic_vector(11 downto 0);		--pozice irc_i
@@ -183,7 +192,7 @@ architecture behavioral of rpi_mc_simple_dc is
 	
 	signal income_data_valid: std_logic;
 	
-	signal clk_3M1: std_logic;
+	signal clk_4M17: std_logic;
 	
 	
 	
@@ -202,6 +211,19 @@ begin
 		y => gpio_clk
 	);
 	
+	pll: pll50to200
+	port map (
+		powerdown => '1',
+		clka => pll_clkin,
+		gla => pll_clkout,
+		lock => pll_lock);
+
+	-- the failasfe signal from communication block if CRC is used
+	next_failsafe <= '0';
+
+	reset_async <= not pll_lock or clkmon_fail;
+
+	pll_clkin <= gpio_clk;
 	
 	qcount: qcounter
 	port map (
@@ -227,7 +249,7 @@ begin
 			clock => gpio_clk, 				--50 Mhz clk from gpclk on raspberry
 			sync => pwm_sync,				--counter restarts
 			data_valid => income_data_valid,			
-			failsafe => '0',
+			failsafe => failsafe,
 			--
 			-- pwm config bits & match word
 			--
@@ -242,16 +264,20 @@ begin
 	end generate;
 	
 	
-	div8_map: div8 
+	div12_map: divider
 	port map(
 		--reset => income_data_valid,
 		clk_in => gpio_clk,
-		clk_out => clk_3M1
+		div12 => clk_4M17
 	);
 	
+	-- ADC needs 3.2 MHz clk when powered from +5V Vcc
+	--	     2.0 MHz clk when +2.7V Vcc
+	-- on the input is 4.17Mhz,but this frequency is divided inside adc_reader by 2 to 2.08 Mhz,
+     	--        while we use +3.3V Vcc     
 	adc_reader_map: adc_reader 
 	port map(
-		clk =>clk_3M1,
+		clk =>clk_4M17,
 		adc_reset => adc_reset,
 		adc_miso => adc_miso,
 		adc_channels => adc_channels,
@@ -262,19 +288,6 @@ begin
 		
 	);
 
-	
-	
-	--   pll: pll50to200
-	--     port map (
-	--       powerdown => '1',
-	--       clka => pll_clkin,
-	--       gla => pll_clkout,
-	--       lock => pll_lock);
-	-- --  reset <= not pll_lock;
-	--   reset <= '0';                         -- TODO: apply reset for good failsafe
-                                           -- upon power-on
-	--   clock <= clkm;
-
 	dummy_unused <= gpio2 and gpio3  and gpio4 and
 		gpio5 and gpio6 and
 		gpio12 and gpio13 and gpio14 and
@@ -368,6 +381,41 @@ begin
 			income_data_valid<='1';
 		end if;
 	end process;
-			
+
+	clock_monitor: process (pll_clkout, gpio_clk, clkmon_dly1, clkmon_wdg, clkmon_fail_next)
+	begin
+		if pll_clkout'event and pll_clkout = '1' then
+			clkmon_dly1 <= gpio_clk;
+			clkmon_dly2 <= clkmon_dly1;
+			if clkmon_dly1 = '0' and clkmon_dly2 = '1' then
+				clkmon_wdg <= 6;
+				clkmon_fail_next <= '0';
+			elsif clkmon_wdg > 0 then
+				clkmon_wdg <= clkmon_wdg - 1;
+				clkmon_fail_next <= '0';
+			else
+				clkmon_wdg <= 0;
+				clkmon_fail_next <= '1';
+			end if;
+			clkmon_fail <= clkmon_fail_next;
+		end if;
+	end process;
+
+	async_rst: process (gpio_clk, reset_async, reset_sync)
+	begin
+		if reset_async = '1' then
+			failsafe <= '1';
+		elsif gpio_clk'event and gpio_clk = '1' then
+			failsafe <= next_failsafe or reset_sync;
+		end if;
+	end process;
+
+	sync_rst: process (gpio_clk, reset_async)
+	begin
+		if gpio_clk'event and gpio_clk = '1' then
+			reset_sync <= reset_async;
+		end if;
+	end process;
+
 end behavioral;