X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/a878f480354c01ccb7c4b670638cfdc738902c0c..ee6653b06cc0c19947e2ad3cd675a8e4121c00c6:/pmsm-control/divider.vhdl

diff --git a/pmsm-control/divider.vhdl b/pmsm-control/divider.vhdl
deleted file mode 100644
index 5f9a13f..0000000
--- a/pmsm-control/divider.vhdl
+++ /dev/null
@@ -1,39 +0,0 @@
--- provides frequency division by 12
--- initialy intended to make 4.17Mhz from 50Mhz 
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.util.all;
-
-entity divider is
-
-port (
-	clk_in: in std_logic;
-	div12: out std_logic
-);
-end divider;
-
-
-architecture behavioral of divider is
-	signal count : std_logic_vector (2 downto 0);
-	signal tmp : std_logic;
-begin
-	
-	
-	divider : process 
-	begin
-		wait until (clk_in'event and clk_in='1');
-		if (count(2 downto 1)="11") then
-			count<="000";
-			tmp <= not tmp;
-		else
-			count <= std_logic_vector(unsigned(count) + 1);
-		end if;
-			div12<=tmp;
-    end process divider;
-
-	
-		
-end behavioral;
-