X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/a878f480354c01ccb7c4b670638cfdc738902c0c..ee6653b06cc0c19947e2ad3cd675a8e4121c00c6:/pmsm-control/adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index 219841c..78eceb6 100644
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -52,7 +52,6 @@ architecture behavioral of adc_reader is
 	signal prepared_data: std_logic_vector(71 downto 0);	--consistent data, waiting for clk sync to propagate to output
 	signal m_count_sig: std_logic_vector(8 downto 0);	--measurments count waiting for clk to propagate to output
 	signal first_pass: std_logic;
-	signal div_clk_prev: std_logic;
 begin
 	
 	
@@ -69,9 +68,7 @@ begin
 			reset_re:='1';
 		end if;
 		
-		--rising edge detection of divided clk signal
-		div_clk_prev<=divided_clk;
-		if (divided_clk='1') and (div_clk_prev='0') then
+		if (divided_clk='1') then --instead of divide, single puls is now detected
 		
 		case state is
 			when reset=>