X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/8945272802e6d9bdd317bced4aba96d7ca442e9b..ade9ac01fc3d82eaf5d4e95c51efc238cd31a2af:/pmsm-control/adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index cda8cc7..78eceb6 100644
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -1,4 +1,18 @@
-
+--
+-- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board *
+-- SPI connected multichannel current ADC read and averaging
+--
+-- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
+-- Czech Technical University in Prague
+--
+-- Project supervision and original project idea
+-- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
+--
+-- Related RPi-MI-1 hardware is designed by Petr Porazil,
+-- PiKRON Ltd  <http://www.pikron.com>
+--
+-- license: GNU LGPL and GPLv3+
+--
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -7,13 +21,16 @@ use work.util.all;
 
 entity adc_reader is
 port (
-	clk: in std_logic;					--input clk
-	adc_reset: in std_logic;
+	clk: in std_logic;					--synchronous master clk
+	divided_clk : in std_logic;				--divided clk - value suitable to sourcing voltage
+	adc_reset: in std_logic;				--synchronous reset on rising edge
+	
 	adc_miso: in std_logic;					--spi master in slave out
-	adc_channels: out std_logic_vector (71 downto 0);	--consistent data of 3 channels
 	adc_sclk: out std_logic; 				--spi clk
 	adc_scs: out std_logic;					--spi slave select
 	adc_mosi: out std_logic;				--spi master out slave in
+	
+	adc_channels: out std_logic_vector (71 downto 0);	--consistent data of 3 channels
 	measur_count: out std_logic_vector(8 downto 0)		--number of accumulated measurments
 	
 );
@@ -29,7 +46,7 @@ architecture behavioral of adc_reader is
 	type channel_type is (ch0, ch1, ch2);
 	
 	signal adc_data: std_logic_vector(11 downto 0); 
-	signal adc_rst_old : std_logic_vector(1 downto 0);
+	signal adc_rst_prev : std_logic;
 	signal adc_address: std_logic_vector(2 downto 0);
 	signal cumul_data: std_logic_vector(71 downto 0);	--unconsistent data, containing different amounts of measurments
 	signal prepared_data: std_logic_vector(71 downto 0);	--consistent data, waiting for clk sync to propagate to output
@@ -46,13 +63,13 @@ begin
 		wait until (clk'event and clk='1');
 		
 		--rising edge detection of reset signal
-		adc_rst_old(0)<=adc_reset;
-		adc_rst_old(1)<=adc_rst_old(0);
-		
-		if (adc_rst_old="01") then
+		adc_rst_prev<=adc_reset;
+		if (adc_rst_prev='0') and (adc_reset='1') then
 			reset_re:='1';
 		end if;
 		
+		if (divided_clk='1') then --instead of divide, single puls is now detected
+		
 		case state is
 			when reset=>
 				reset_re:='0'; 			--clear reset flag
@@ -219,6 +236,9 @@ begin
 					state<=f1;
 				end if;
 		end case;
+		
+		end if;
+		
 	end process;