X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/6841e483f0b370a6ea2b41c958945d3db9285c90..1c8eb36a8a3c7e271cc07ee6d25120c950fb0160:/pmsm-control/div128.vhdl

diff --git a/pmsm-control/div128.vhdl b/pmsm-control/div128.vhdl
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+-- provides frequency division by 12
+-- initialy intended to make 4.17Mhz from 50Mhz 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.util.all;
+
+entity div128 is
+
+port (
+	clk_in: in std_logic;
+	rst: in std_logic;
+	fail_safe: out std_logic
+);
+end div128;
+
+
+architecture behavioral of div128 is
+	signal count : std_logic_vector (6 downto 0);
+	signal rst_prev: std_logic;
+begin
+	
+	
+	seq : process 
+	begin
+		wait until (clk_in'event and clk_in='1');
+		rst_prev <= rst;
+		if rst='1' and rst_prev='0' then
+			count <= "0000000";
+			fail_safe <= '0';
+		else
+			count <= std_logic_vector(unsigned(count) + 1);
+		end if;
+		
+		if count = "1111111" then
+			fail_safe <= '1';
+		else 
+			fail_safe <= '0';
+		end if;
+	end process;
+
+	
+		
+end behavioral;
+