X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/5e9d551775408b98dd40058d4ba5ae0603cb3752..ee6653b06cc0c19947e2ad3cd675a8e4121c00c6:/pmsm-control/rpi_pmsm_control.vhdl diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl index f8e8bd5..13ffb97 100644 --- a/pmsm-control/rpi_pmsm_control.vhdl +++ b/pmsm-control/rpi_pmsm_control.vhdl @@ -1,13 +1,22 @@ -- --- * LXPWR slave part * --- common sioreg & common counter for several ADC&PWM blocks +-- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board * +-- The toplevel component file -- --- part of LXPWR motion control board (c) PiKRON Ltd --- idea by Pavel Pisa PiKRON Ltd --- code by Marek Peca --- 01/2013 +-- (c) 2015 Martin Prudek +-- Czech Technical University in Prague -- --- license: GNU GPLv3 +-- Project supervision and original project idea +-- idea by Pavel Pisa +-- +-- Related RPi-MI-1 hardware is designed by Petr Porazil, +-- PiKRON Ltd +-- +-- VHDL design reuses some components and concepts from +-- LXPWR motion power stage board and LX_RoCoN system +-- developed at PiKRON Ltd with base code implemented +-- by Marek Peca +-- +-- license: GNU LGPL and GPLv3+ -- library ieee; @@ -135,16 +144,24 @@ architecture behavioral of rpi_pmsm_control is end component; --frequency division by 12 - component divider is - port ( - clk_in: in std_logic; - div12: out std_logic + component cnt_div is + generic ( + cnt_width_g : natural := 4 + ); + port + ( + clk_i : in std_logic; --clk to divide + en_i : in std_logic; --enable bit? + reset_i : in std_logic; --asynch. reset + ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value + q_out_o : out std_logic --generates puls when counter underflows ); end component; component adc_reader is port ( clk: in std_logic; --input clk + divided_clk : in std_logic; --divided clk - value suitable to sourcing voltage adc_reset: in std_logic; adc_miso: in std_logic; --spi master in slave out adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels @@ -157,7 +174,6 @@ architecture behavioral of rpi_pmsm_control is end component; - signal adc_reset : std_logic; signal adc_channels: std_logic_vector(71 downto 0); signal adc_m_count: std_logic_vector(8 downto 0); @@ -170,7 +186,10 @@ architecture behavioral of rpi_pmsm_control is signal reset_sync, reset_async: std_logic; signal failsafe, next_failsafe: std_logic; + --RPi SPI interface signals named aliases + signal spi_clk, spi_ce, spi_mosi, spi_miso : std_logic; signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin + --signal pwm_in, pwm_dir_in: std_logic; signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi signal position: std_logic_vector(31 downto 0); --pozice z qcounteru @@ -185,6 +204,7 @@ architecture behavioral of rpi_pmsm_control is signal pwm_match: pwm_res_type; --point of reversion of pwm output, 0 to 2047 signal pwm_count: std_logic_vector (pwm_width-1 downto 0); --counter, 0 to 2047 + signal pwm_sync_at_next: std_logic; signal pwm_sync: std_logic; signal pwm_en_p: std_logic_vector(1 to 3); signal pwm_en_n: std_logic_vector(1 to 3); @@ -249,7 +269,7 @@ begin port map ( clock => gpio_clk, --50 Mhz clk from gpclk on raspberry sync => pwm_sync, --counter restarts - data_valid => income_data_valid, + data_valid => pwm_sync_at_next, failsafe => failsafe, -- -- pwm config bits & match word @@ -265,11 +285,13 @@ begin end generate; - div12_map: divider + div12_map: cnt_div port map( - --reset => income_data_valid, - clk_in => gpio_clk, - div12 => clk_4M17 + clk_i => gpio_clk, + en_i =>'1', + reset_i =>'0', + ratio_i =>"1101", --POZN.: counter detekuje cnt<=1 + q_out_o =>clk_4M17 ); -- ADC needs 3.2 MHz clk when powered from +5V Vcc @@ -278,8 +300,9 @@ begin -- while we use +3.3V Vcc adc_reader_map: adc_reader port map( - clk =>clk_4M17, - adc_reset => adc_reset, + clk => gpio_clk, + divided_clk => clk_4M17, + adc_reset => income_data_valid, --reset at each SPI cycle,TODO: replace with PLL reset adc_miso => adc_miso, adc_channels => adc_channels, adc_sclk => adc_sclk, @@ -289,7 +312,7 @@ begin ); - dummy_unused <= gpio2 and gpio3 and gpio4 and + dummy_unused <= gpio2 and gpio3 and gpio5 and gpio6 and gpio12 and gpio13 and gpio14 and gpio15 and gpio16 and gpio19 and @@ -303,12 +326,16 @@ begin dip_sw(1) and dip_sw(2) and dip_sw(3) and irc_a and irc_b and gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and - gpio8 and gpio11 and gpio7 and gpio10 and + gpio8 and ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0; rs485_txd <= '1'; rs485_dir <= '0'; + spi_clk <= gpio11; + spi_ce <= gpio7; + spi_mosi <= gpio10; + gpio9 <= spi_miso; pwm(1) <= pwm_sig(1) and dip_sw(1); pwm(2) <= pwm_sig(2) and dip_sw(2); @@ -327,8 +354,16 @@ begin process begin wait until (gpio_clk'event and gpio_clk='1'); - IF(pwm_count = pwm_period) THEN - --end of period reached + IF pwm_count = std_logic_vector(unsigned(pwm_period) - 1) THEN + --end of period nearly reached + --fetch new pwm match data + pwm_sync_at_next <= '1'; + else + pwm_sync_at_next <= '0'; + end if; + + if pwm_sync_at_next='1' then + --end of period reached pwm_count <= (others=>'0'); --reset counter pwm_sync <= '1'; -- inform PWM logic about new period start ELSE --end of period not reached @@ -343,22 +378,22 @@ begin wait until (gpio_clk'event and gpio_clk='1'); --SCLK edge detection - spiclk_old(0)<=gpio11; + spiclk_old(0)<=spi_clk; spiclk_old(1)<=spiclk_old(0); --SS edge detection - ce0_old(0)<=gpio7; + ce0_old(0)<=spi_ce; ce0_old(1)<=ce0_old(0); if (spiclk_old="01") then --rising edge, faze cteni - if (gpio7 = '0') then -- SPI CS must be selected + if (spi_ce = '0') then -- SPI CS must be selected -- shift serial data into dat_reg on each rising edge -- of SCK, MSB first - dat_reg(127 downto 0) <= dat_reg(126 downto 0) & gpio10; + dat_reg(127 downto 0) <= dat_reg(126 downto 0) & spi_mosi; end if; elsif (spiclk_old="10" ) then --falling edge, faze zapisu - if (gpio7 = '0') then - gpio9 <= dat_reg(127); --zapisujeme nejdriv MSB + if (spi_ce = '0') then + spi_miso <= dat_reg(127); --zapisujeme nejdriv MSB end if; end if; @@ -372,16 +407,14 @@ begin dat_reg(80 downto 72) <=adc_m_count(8 downto 0); --count of measurments --data order schould be: ch2 downto ch0 downto ch1 dat_reg(71 downto 0) <= adc_channels(71 downto 0); --current mesurments - adc_reset<='0'; --remove reset flag, and wait on its rising edge + spi_miso <= position(31); --prepare the first bit on SE activation elsif (ce0_old = "01") then --rising edge of SS, we should read the data - adc_reset<='1'; pwm_en_p(1 to 3)<=dat_reg(126 downto 124); pwm_en_n(1 to 3)<=dat_reg(123 downto 121); - --11 bit pwm TODO: make it generic - pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(66 downto 56); - pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(55 downto 45); - -- 12 + 11 Unused - pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(42 downto 32); + --usable for up to 16-bit PWM duty cycle resolution (pwm_width): + pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(pwm_width+31 downto 32); + pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(pwm_width+15 downto 16); + pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(pwm_width-1 downto 0); income_data_valid<='1'; end if; end process;