X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/5e9d551775408b98dd40058d4ba5ae0603cb3752..41ad6fb58e07390cc1807e43d0de04d670c5719e:/pmsm-control/rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index f8e8bd5..413f11c 100644
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -1,13 +1,22 @@
 --
--- * LXPWR slave part *
---  common sioreg & common counter for several ADC&PWM blocks
+-- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board *
+-- The toplevel component file
 --
--- part of LXPWR motion control board (c) PiKRON Ltd
--- idea by Pavel Pisa PiKRON Ltd <pisa@cmp.felk.cvut.cz>
--- code by Marek Peca <mp@duch.cz>
--- 01/2013
+-- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
+-- Czech Technical University in Prague
 --
--- license: GNU GPLv3
+-- Project supervision and original project idea
+-- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
+--
+-- Related RPi-MI-1 hardware is designed by Petr Porazil,
+-- PiKRON Ltd  <http://www.pikron.com>
+--
+-- VHDL design reuses some components and concepts from
+-- LXPWR motion power stage board and LX_RoCoN system
+-- developed at PiKRON Ltd with base code implemented
+-- by Marek Peca <hefaistos@gmail.com>
+--
+-- license: GNU LGPL and GPLv3+
 --
 
 library ieee;
@@ -145,6 +154,7 @@ architecture behavioral of rpi_pmsm_control is
 	component adc_reader is
 	port (
 		clk: in std_logic;					--input clk
+		divided_clk : in std_logic;				--divided clk - value suitable to sourcing voltage
 		adc_reset: in std_logic;
 		adc_miso: in std_logic;					--spi master in slave out
 		adc_channels: out std_logic_vector (35 downto 0);	--consistent data of 3 channels
@@ -170,7 +180,10 @@ architecture behavioral of rpi_pmsm_control is
 	signal reset_sync, reset_async: std_logic;
 	signal failsafe, next_failsafe: std_logic;
 
+	--RPi SPI interface signals named aliases
+	signal spi_clk, spi_ce, spi_mosi, spi_miso : std_logic;
 	signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
+
 	--signal pwm_in, pwm_dir_in: std_logic;
 	signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
 	signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
@@ -278,7 +291,8 @@ begin
      	--        while we use +3.3V Vcc     
 	adc_reader_map: adc_reader 
 	port map(
-		clk =>clk_4M17,
+		clk => gpio_clk,
+		divided_clk => clk_4M17,
 		adc_reset => adc_reset,
 		adc_miso => adc_miso,
 		adc_channels => adc_channels,
@@ -289,7 +303,7 @@ begin
 		
 	);
 
-	dummy_unused <= gpio2 and gpio3  and gpio4 and
+	dummy_unused <= gpio2 and gpio3 and
 		gpio5 and gpio6 and
 		gpio12 and gpio13 and gpio14 and
 		gpio15 and gpio16 and gpio19 and
@@ -303,12 +317,16 @@ begin
 		dip_sw(1) and dip_sw(2) and dip_sw(3) and
 		irc_a and irc_b and
 		gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
-		gpio8  and gpio11 and gpio7 and gpio10 and
+		gpio8  and
 		ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
 			
 	rs485_txd <= '1';
 	rs485_dir <= '0';
 
+	spi_clk <= gpio11;
+	spi_ce <= gpio7;
+	spi_mosi <= gpio10;
+	gpio9 <= spi_miso;
 
 	pwm(1) <= pwm_sig(1) and dip_sw(1);
 	pwm(2) <= pwm_sig(2) and dip_sw(2);
@@ -343,22 +361,22 @@ begin
 		wait until (gpio_clk'event and gpio_clk='1');
 		
 		--SCLK edge detection
-		spiclk_old(0)<=gpio11;
+		spiclk_old(0)<=spi_clk;
 		spiclk_old(1)<=spiclk_old(0);
 		
 		--SS edge detection
-		ce0_old(0)<=gpio7;
+		ce0_old(0)<=spi_ce;
 		ce0_old(1)<=ce0_old(0);
 		
 		if (spiclk_old="01") then --rising edge, faze cteni
-			if (gpio7 = '0') then             -- SPI CS must be selected
+			if (spi_ce = '0') then             -- SPI CS must be selected
 				-- shift serial data into dat_reg on each rising edge
 				-- of SCK, MSB first
-				dat_reg(127 downto 0) <= dat_reg(126 downto 0) & gpio10;
+				dat_reg(127 downto 0) <= dat_reg(126 downto 0) & spi_mosi;
 				end if;
 		elsif (spiclk_old="10" ) then --falling edge, faze zapisu
-			if (gpio7 = '0') then
-				gpio9 <= dat_reg(127); --zapisujeme nejdriv MSB
+			if (spi_ce = '0') then
+				spi_miso <= dat_reg(127); --zapisujeme nejdriv MSB
 			end if;
 		end if;
 		
@@ -372,6 +390,7 @@ begin
 			dat_reg(80 downto 72) <=adc_m_count(8 downto 0);   	--count of measurments
 			--data order schould be: ch2 downto ch0 downto ch1
 			dat_reg(71 downto 0) <= adc_channels(71 downto 0); 	--current mesurments
+			spi_miso <= position(31); 		--prepare the first bit on SE activation
 			adc_reset<='0'; --remove reset flag, and wait on its rising edge
 		elsif (ce0_old = "01") then --rising edge of SS, we should read the data
 			adc_reset<='1';