X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/44c23daa6e0d5d35e892b79684b239c1a0e67f25:/pmsm-control/div8.vhdl..20d2ad19b7050e37e1ebdb9f13c7027eabd151a2:/pmsm-control/divider.vhdl

diff --git a/pmsm-control/div8.vhdl b/pmsm-control/divider.vhdl
similarity index 58%
rename from pmsm-control/div8.vhdl
rename to pmsm-control/divider.vhdl
index f243183..5f9a13f 100644
--- a/pmsm-control/div8.vhdl
+++ b/pmsm-control/divider.vhdl
@@ -1,33 +1,36 @@
-
+-- provides frequency division by 12
+-- initialy intended to make 4.17Mhz from 50Mhz 
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 
-entity div8 is
+entity divider is
 
 port (
 	clk_in: in std_logic;
-	clk_out: out std_logic
+	div12: out std_logic
 );
-end div8;
+end divider;
 
 
-architecture behavioral of div8 is
+architecture behavioral of divider is
 	signal count : std_logic_vector (2 downto 0);
+	signal tmp : std_logic;
 begin
 	
 	
 	divider : process 
 	begin
 		wait until (clk_in'event and clk_in='1');
-		if (count="111") then
+		if (count(2 downto 1)="11") then
 			count<="000";
+			tmp <= not tmp;
 		else
 			count <= std_logic_vector(unsigned(count) + 1);
 		end if;
-			clk_out <= count(2);
+			div12<=tmp;
     end process divider;