X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/376e0d0c5e8a7ce2739c2aba7793b9f9eeff307f..41ad6fb58e07390cc1807e43d0de04d670c5719e:/pmsm-control/rpi_pmsm_control.vhdl diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl index a74bc2b..413f11c 100644 --- a/pmsm-control/rpi_pmsm_control.vhdl +++ b/pmsm-control/rpi_pmsm_control.vhdl @@ -1,5 +1,5 @@ -- --- * Raspberry Pi BLDC/PMSM motor control design for RPi-MC-1 board * +-- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board * -- The toplevel component file -- -- (c) 2015 Martin Prudek @@ -8,7 +8,7 @@ -- Project supervision and original project idea -- idea by Pavel Pisa -- --- Related RPi-MC-1 hardware is designed by Petr Porazil, +-- Related RPi-MI-1 hardware is designed by Petr Porazil, -- PiKRON Ltd -- -- VHDL design reuses some components and concepts from @@ -154,6 +154,7 @@ architecture behavioral of rpi_pmsm_control is component adc_reader is port ( clk: in std_logic; --input clk + divided_clk : in std_logic; --divided clk - value suitable to sourcing voltage adc_reset: in std_logic; adc_miso: in std_logic; --spi master in slave out adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels @@ -290,7 +291,8 @@ begin -- while we use +3.3V Vcc adc_reader_map: adc_reader port map( - clk =>clk_4M17, + clk => gpio_clk, + divided_clk => clk_4M17, adc_reset => adc_reset, adc_miso => adc_miso, adc_channels => adc_channels, @@ -388,6 +390,7 @@ begin dat_reg(80 downto 72) <=adc_m_count(8 downto 0); --count of measurments --data order schould be: ch2 downto ch0 downto ch1 dat_reg(71 downto 0) <= adc_channels(71 downto 0); --current mesurments + spi_miso <= position(31); --prepare the first bit on SE activation adc_reset<='0'; --remove reset flag, and wait on its rising edge elsif (ce0_old = "01") then --rising edge of SS, we should read the data adc_reset<='1';