X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/rpi-motor-control.git/blobdiff_plain/0f963bbd68c35a3c550a82cc23590f46e667ebdf..41ad6fb58e07390cc1807e43d0de04d670c5719e:/pmsm-control/adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index 8f2f2c5..219841c 100644
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -21,13 +21,16 @@ use work.util.all;
 
 entity adc_reader is
 port (
-	clk: in std_logic;					--input clk
-	adc_reset: in std_logic;
+	clk: in std_logic;					--synchronous master clk
+	divided_clk : in std_logic;				--divided clk - value suitable to sourcing voltage
+	adc_reset: in std_logic;				--synchronous reset on rising edge
+	
 	adc_miso: in std_logic;					--spi master in slave out
-	adc_channels: out std_logic_vector (71 downto 0);	--consistent data of 3 channels
 	adc_sclk: out std_logic; 				--spi clk
 	adc_scs: out std_logic;					--spi slave select
 	adc_mosi: out std_logic;				--spi master out slave in
+	
+	adc_channels: out std_logic_vector (71 downto 0);	--consistent data of 3 channels
 	measur_count: out std_logic_vector(8 downto 0)		--number of accumulated measurments
 	
 );
@@ -43,12 +46,13 @@ architecture behavioral of adc_reader is
 	type channel_type is (ch0, ch1, ch2);
 	
 	signal adc_data: std_logic_vector(11 downto 0); 
-	signal adc_rst_old : std_logic_vector(1 downto 0);
+	signal adc_rst_prev : std_logic;
 	signal adc_address: std_logic_vector(2 downto 0);
 	signal cumul_data: std_logic_vector(71 downto 0);	--unconsistent data, containing different amounts of measurments
 	signal prepared_data: std_logic_vector(71 downto 0);	--consistent data, waiting for clk sync to propagate to output
 	signal m_count_sig: std_logic_vector(8 downto 0);	--measurments count waiting for clk to propagate to output
 	signal first_pass: std_logic;
+	signal div_clk_prev: std_logic;
 begin
 	
 	
@@ -60,13 +64,15 @@ begin
 		wait until (clk'event and clk='1');
 		
 		--rising edge detection of reset signal
-		adc_rst_old(0)<=adc_reset;
-		adc_rst_old(1)<=adc_rst_old(0);
-		
-		if (adc_rst_old="01") then
+		adc_rst_prev<=adc_reset;
+		if (adc_rst_prev='0') and (adc_reset='1') then
 			reset_re:='1';
 		end if;
 		
+		--rising edge detection of divided clk signal
+		div_clk_prev<=divided_clk;
+		if (divided_clk='1') and (div_clk_prev='0') then
+		
 		case state is
 			when reset=>
 				reset_re:='0'; 			--clear reset flag
@@ -233,6 +239,9 @@ begin
 					state<=f1;
 				end if;
 		end case;
+		
+		end if;
+		
 	end process;