zjednoduseni vzorkovani spi hodin gpio hodinami. Otestovano a funkcni. (SCLK 500...

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index 7cdfac3172c895f5603507780e0cf6804da0947e..75ed7271ae04750fb9e7c2fd55832676b22a4390 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -121,8 +121,8 @@ architecture behavioral of rpi_mc_simple_dc is
        --"0000000100100011010001010110011110001001101010111100110111101111";
                --(others=>'0'); --registr pro SPI
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
-       signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
-       signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
+       --signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
+       --signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
        signal ce0_int: std_logic;
        
        --  attribute syn_noprune of gpio2 : signal is true;
@@ -211,28 +211,31 @@ begin
        pwm(3) <= '0';
 
        
-       process(gpio_clk)
-       begin
-               if gpio_clk= '1' and gpio_clk'event then
-                       spiclk_old_lvl<=spi_clk;
-               end if;
-       end process;
-       spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
-       spi_clk_fall <= (not spi_clk) and spiclk_old_lvl; 
+--     process(gpio_clk)
+--     begin
+--             if gpio_clk= '1' and gpio_clk'event then
+--                     spiclk_old_lvl<=spi_clk;
+--             end if;
+--     end process;
+--     spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
+--     spi_clk_fall <= (not spi_clk) and spiclk_old_lvl; 
  
   
-       process(spi_clk_fall,spi_clk_rise)
+--     process(spi_clk_fall,spi_clk_rise)
+       process
        begin
-               if (rising_edge(spi_clk_rise)) then --rising edge, faze cteni 
+               wait until (gpio_clk'event and gpio_clk='1');
+               if (spi_clk='1' and spiclk_old_lvl='0') then --rising edge, faze cteni
                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                                dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
+                               spiclk_old_lvl <= '1';
                                end if;
-               elsif (rising_edge(spi_clk_fall) ) then --falling edge, faze zapisu
+               elsif (spi_clk='0' and spiclk_old_lvl='1' ) then --falling edge, faze zapisu
                        if (gpio7 = '0') then
                                gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
-                               
+                               spiclk_old_lvl <= '0';
                        end if;
                end if;
        end process;