GPCLK frequency from RPi increased from 2Mhz to 50Mhz. To keep clk frequency for...

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index 3d188e0c6617d21043fdbc5b835224e6bef3b35c..1591fba1f328e56bac2bb445912d3783f256a425 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -133,6 +133,14 @@ architecture behavioral of rpi_mc_simple_dc is
        );
        end component;
        
+       component div8 is
+       port (
+               --reset: in std_logic;
+               clk_in: in std_logic;
+               clk_out: out std_logic
+       );
+       end component;
+       
        
        type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
        signal state : state_type;
@@ -166,6 +174,8 @@ architecture behavioral of rpi_mc_simple_dc is
        
        signal income_data_valid: std_logic;
        
+       signal clk_3M1: std_logic;
+       
        
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
@@ -222,6 +232,14 @@ begin
        end generate;
        
        
+       div8_map: div8 
+       port map(
+               --reset => income_data_valid,
+               clk_in => gpio_clk,
+               clk_out => clk_3M1
+       );
+
+       
        
        --   pll: pll50to200
        --     port map (
@@ -328,7 +346,7 @@ begin
                variable reset_re: std_logic:='0';
                variable reset_count: integer:=0;
        begin
-               wait until (gpio_clk'event and gpio_clk='1');
+               wait until (clk_3M1'event and clk_3M1='1');
                
                --reset rising edge detection
                adc_rst_old(0)<=adc_reset;