Simple frequency divider replaced with more complex counter.

[fpga/rpi-motor-control.git] / pmsm-control / adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index 219841c2c93a038aa1e6cbd37bcd311e4fe53db9..78eceb6451dc28c302d397d31a08e31151555cbc 100644 (file)
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -52,7 +52,6 @@ architecture behavioral of adc_reader is
        signal prepared_data: std_logic_vector(71 downto 0);    --consistent data, waiting for clk sync to propagate to output
        signal m_count_sig: std_logic_vector(8 downto 0);       --measurments count waiting for clk to propagate to output
        signal first_pass: std_logic;
-       signal div_clk_prev: std_logic;
 begin
        
        
@@ -69,9 +68,7 @@ begin
                        reset_re:='1';
                end if;
                
-               --rising edge detection of divided clk signal
-               div_clk_prev<=divided_clk;
-               if (divided_clk='1') and (div_clk_prev='0') then
+               if (divided_clk='1') then --instead of divide, single puls is now detected
                
                case state is
                        when reset=>