Changed positions of PWM duty cycle bits in SPI communication.

[fpga/rpi-motor-control.git] / pmsm-control / test_sw / main_pmsm.c

diff --git a/pmsm-control/test_sw/main_pmsm.c b/pmsm-control/test_sw/main_pmsm.c
index 5759c970e92d0ceaf0fc745ba9bd565d4bdebf6f..4e64f957868c6c3e2dddf3499276676556c270b9 100644 (file)
--- a/pmsm-control/test_sw/main_pmsm.c
+++ b/pmsm-control/test_sw/main_pmsm.c
@@ -185,17 +185,18 @@ void prepare_tx(uint8_t * tx){
         * bit 89 - shutdown3
         *      .
         *      .
+        *      Unused
         *      .
-        * bits 66 .. 56 - match PWM1
-        * bits 55 .. 45 - match PWM2
-        * bit 11,12 - Unused
-        * bits 42 .. 32  - match PWM3
+        *      .
+        * bits 47 .. 32 - match PWM1
+        * bits 31 .. 16 - match PWM2
+        * bits 15 .. 0  - match PWM3
         */
 
 
        uint16_t tmp;
 
-       /* keep the cap*/
+       /* keep the 11-bit cap*/
 
        if (rps.pwm1>2047) rps.pwm1=2047;
        if (rps.pwm2>2047) rps.pwm2=2047;
@@ -203,19 +204,19 @@ void prepare_tx(uint8_t * tx){
 
        tx[0]=rps.test; /*bit 94 - enable PWM1*/
 
+       /*now we have to switch the bytes due to endianess */
+       /* ARMv6 & ARMv7 instructions are little endian */
        /*pwm1*/
-       tx[7]=(tx[7] & 0xF8) | (0x07 & ((uint8_t*)&rps.pwm1)[1]); /*MSB*/
-       tx[8]=((uint8_t*)&rps.pwm1)[0]; /*LSB*/
+       tx[10]=((uint8_t*)&rps.pwm1)[1]; /*MSB*/
+       tx[11]=((uint8_t*)&rps.pwm1)[0]; /*LSB*/
 
        /*pwm2*/
-       tmp=rps.pwm2;
-       tmp<<=5;
-       tx[9]=((uint8_t*)&tmp)[1]; /*MSB*/
-       tx[10]=(tx[10] & 0x1F) | (0xE0 & ((uint8_t*)&tmp)[0]); /*LSB*/
+       tx[12]=((uint8_t*)&rps.pwm2)[1]; /*MSB*/
+       tx[13]=((uint8_t*)&rps.pwm2)[0]; /*LSB*/
 
        /*pwm3*/
-       tx[10]=(tx[10] & 0xF8) | (0x07 & ((uint8_t*)&rps.pwm3)[1]); /*MSB*/
-       tx[11]=((uint8_t*)&rps.pwm3)[0]; /*LSB*/
+       tx[14]=((uint8_t*)&rps.pwm3)[1]; /*MSB*/
+       tx[15]=((uint8_t*)&rps.pwm3)[0]; /*LSB*/
 
 
 }