signal pwm_in, pwm_dir_in: std_logic;
signal spi_clk: std_logic;
signal gpio_clk: std_logic;
- signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):="10101010";
+ signal dat_reg : STD_LOGIC_VECTOR (64 downto 0):=(others=>'0'); --inicializace - funguje?
--"0000000100100011010001010110011110001001101010111100110111101111";
--(others=>'0'); --registr pro SPI
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
--signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
--signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
- signal ce0_int: std_logic;
+ signal ce0_old: std_logic;
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
y => gpio_clk
);
- --zesileni signalu CE0
- copyclk3: CLKINT
- port map (
- a => gpio7,
- y => ce0_int
- );
qcount: qcounter
port map (
if (gpio7 = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
- dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
+ dat_reg(63 downto 0) <= dat_reg(62 downto 0) & gpio10;
spiclk_old_lvl <= '1';
end if;
elsif (spi_clk='0' and spiclk_old_lvl='1' ) then --falling edge, faze zapisu
if (gpio7 = '0') then
- gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
+ gpio9 <= dat_reg(63); --zapisujeme nejdriv MSB
spiclk_old_lvl <= '0';
end if;
end if;
+
+ if (gpio7='1' and ce0_old = '0') then --nastupna hrana slave select
+ ce0_old <= '1';
+ elsif (gpio7='0' and ce0_old = '1') then --sestupna hrana SS, pripravime data pro prenos
+ dat_reg(63 downto 32) <= position(31 downto 0); --pozice
+ dat_reg(31 downto 0) <= (others => '0'); --zbytek zatim nuly
+ ce0_old <= '0';
+ end if;
end process;
+
+
end behavioral;
+