);
end component;
- signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
+ signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
signal pwm_in, pwm_dir_in: std_logic;
signal spi_clk: std_logic;
signal gpio_clk: std_logic;
- signal dat_reg : STD_LOGIC_VECTOR (64 downto 0):=(others=>'0'); --inicializace - funguje?
- --"0000000100100011010001010110011110001001101010111100110111101111";
- --(others=>'0'); --registr pro SPI
+ signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
+ signal spi_ctrl : std_logic_vector (96 downto 0); --ctrl reg for spi, in use when thers no falling edge of CS
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
--signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
--signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
- signal ce0_old: std_logic;
+ signal ce0_old: std_logic_vector(1 downto 0);
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
-- process(spi_clk_fall,spi_clk_rise)
process
begin
- wait until (gpio_clk'event and gpio_clk='1');
- if (spi_clk='1' and spiclk_old_lvl='0') then --rising edge, faze cteni
+ --position is obtained on rising edge -> we should write it on falling edge
+ wait until (gpio_clk'event and gpio_clk='0');
+
+ spiclk_old(0)<=spi_clk;
+ spiclk_old(1)<=spiclk_old(0);
+
+ ce0_old(0)<=gpio7;
+ ce0_old(1)<=ce0_old(0);
+
+ if (spiclk_old="01") then --rising edge, faze cteni
if (gpio7 = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
- dat_reg(63 downto 0) <= dat_reg(62 downto 0) & gpio10;
- spiclk_old_lvl <= '1';
+ dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
+ --spi_ctrl(96 downto 0) <= spi_ctrl(95 downto 0) & spi_ctrl(96); --shift ctrl reg
end if;
- elsif (spi_clk='0' and spiclk_old_lvl='1' ) then --falling edge, faze zapisu
+ elsif (spiclk_old="10" ) then --falling edge, faze zapisu
if (gpio7 = '0') then
- gpio9 <= dat_reg(63); --zapisujeme nejdriv MSB
- spiclk_old_lvl <= '0';
+ gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
end if;
end if;
- if (gpio7='1' and ce0_old = '0') then --nastupna hrana slave select
- ce0_old <= '1';
- elsif (gpio7='0' and ce0_old = '1') then --sestupna hrana SS, pripravime data pro prenos
- dat_reg(63 downto 32) <= position(31 downto 0); --pozice
- dat_reg(31 downto 0) <= (others => '0'); --zbytek zatim nuly
- ce0_old <= '0';
+
+ --sestupna hrana SS, pripravime data pro prenos-prenos zacina nebo zacatek dalsiho ramce
+ if ((ce0_old = "10") ) then
+ dat_reg(95 downto 64) <= position(31 downto 0); --pozice
+ dat_reg(63 downto 0) <= (others => '1'); --zbytek zatim nuly
+ --spiclk_old <= "00"; --bez tohoto prirazeni chodila v ~12% chybna data
+ --no falling edge conroll
+ --spi_ctrl(96 downto 1) <=(others=>'0');
+ --spi_ctrl(0)<='1';
end if;
end process;