);
end component;
+ component dff3 is
+ port(
+ clk_i : in std_logic;
+ d_i : in std_logic;
+ q_o : out std_logic
+ );
+ end component;
+
signal adc_channels: std_logic_vector(71 downto 0);
signal adc_m_count: std_logic_vector(8 downto 0);
-- irc signals processing
signal irc_i_prev: std_logic;
+ --filetered irc signals
+ signal irc_a_dff3: std_logic;
+ signal irc_b_dff3: std_logic;
+
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
-- attribute syn_keep of gpio2 : signal is true;
port map (
clock => gpio_clk,
reset => '0',
- a0 => irc_a,
- b0 => irc_b,
+ a0 => irc_a_dff3,
+ b0 => irc_b_dff3,
qcount => position,
a_rise => open,
a_fall => open,
measur_count => adc_m_count
);
+
+ dff3_a: dff3
+ port map(
+ clk_i => gpio_clk,
+ d_i => irc_a,
+ q_o => irc_a_dff3
+ );
+
+ dff3_b: dff3
+ port map(
+ clk_i => gpio_clk,
+ d_i => irc_b,
+ q_o => irc_b_dff3
+ );
dummy_unused <= gpio2 and gpio3 and
gpio5 and gpio6 and