Added ADC reset after each FPGA<->RPi transfer. ADC channels manipulation improved.

[fpga/rpi-motor-control.git] / pmsm-control / adc_reader.vhdl

diff --git a/pmsm-control/adc_reader.vhdl b/pmsm-control/adc_reader.vhdl
index 3a534460d14a6242184d0be1241ccbe0cf26d4fa..c792525935cc87b4b6da1a2375d04a0783bccdfa 100644 (file)
--- a/pmsm-control/adc_reader.vhdl
+++ b/pmsm-control/adc_reader.vhdl
@@ -29,8 +29,7 @@ architecture behavioral of adc_reader is
        
        signal adc_data: std_logic_vector(11 downto 0); 
        signal adc_rst_old : std_logic_vector(1 downto 0);
-       signal adc_address: std_logic_vector(8 downto 0);
-       
+       signal adc_address: std_logic_vector(2 downto 0);
 begin
        
        
@@ -38,11 +37,11 @@ begin
                variable data_ready : std_logic;
                variable channel: channel_type;
                variable reset_re: std_logic:='0';
-               variable reset_count: integer:=0;
+               variable reset_count: std_logic_vector (3 downto 0);
        begin
                wait until (clk'event and clk='1');
                
-               --reset rising edge detection
+               --rising edge detection of reset signal
                adc_rst_old(0)<=adc_reset;
                adc_rst_old(1)<=adc_rst_old(0);
                
@@ -52,23 +51,19 @@ begin
                
                case state is
                        when reset=>
-                               reset_re:='0'; --clear reset flag
-                               adc_scs<='1'; --active-low SS
-                               adc_sclk<='0'; --lower clock
-                               data_ready:='0'; 
-                               --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
-                               adc_address<="001101010";
-                               channel:=ch0;
-                               adc_channels(35 downto 0)<=(others=>'1'); --for debug only - remove this line!
-                               adc_data(11 downto 0)<=(others=>'1');
-                               reset_count:=0;
+                               reset_re:='0';                  --clear reset flag
+                               adc_scs<='1';                   --active-low SS
+                               adc_sclk<='0';                  --lower clock
+                               data_ready:='0';                --mark data as unprepared
+                               channel:=ch0;                   --prepare channel0
+                               adc_address<="001";             --set its address
+                               reset_count:="0000";
                                state<=rst_wait;
                        when rst_wait=>
-                               if (reset_count<10) then
-                                       reset_count:=reset_count+1;
-                                       if (reset_count=7) then
-                                               adc_scs<='0'; --give the adc some time to prepare before trensfer
-                                       end if;
+                               if (reset_count/="1111") then
+                                       reset_count:=std_logic_vector(unsigned(reset_count)+1);
+                                       --give the adc some time to prepare before transfer
+                                       adc_scs<=not reset_count(3); 
                                else
                                        state<=f1;
                                end if;
@@ -82,7 +77,7 @@ begin
                                state<=f2;
                        when f2=> --2nd falling edge
                                adc_sclk<='0';
-                               adc_mosi<=adc_address(8); --A2 address
+                               adc_mosi<=adc_address(2); --A2 address
                                state<=r2;
                        when r2=> --2nd rising edge (adc gets A2 address)
                                adc_sclk<='1';
@@ -90,7 +85,7 @@ begin
                                state<=f3;
                        when f3=> --3rd falling edge 
                                adc_sclk<='0';
-                               adc_mosi<=adc_address(7); --A1 address
+                               adc_mosi<=adc_address(1); --A1 address
                                state<=r3;
                        when r3=> --rising edge
                                adc_sclk<='1';
@@ -98,9 +93,7 @@ begin
                                state<=f4;      
                        when f4=> --4th falling edge
                                adc_sclk<='0';
-                               adc_mosi<=adc_address(6); --A0 address
-                               --shift the addresses
-                               adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6); 
+                               adc_mosi<=adc_address(0); --A0 address 
                                state<=r4;
                        when r4=> --rising edge
                                adc_sclk<='1';
@@ -132,15 +125,15 @@ begin
                                        case channel is
                                                when ch0=>
                                                        adc_channels(35 downto 24)<=adc_data(11 downto 0);
-                                                       --adc_channels(35 downto 24)<=(others=>'0');
+                                                       adc_address<="101";     --ch1 address
                                                        channel:=ch1;
                                                when ch1=>
                                                        adc_channels(23 downto 12)<=adc_data(11 downto 0);
-                                                       --adc_channels(23 downto 12)<=(others=>'1');
+                                                       adc_address<="010";     --ch2 address
                                                        channel:=ch2;
                                                when ch2=>
                                                        adc_channels(11 downto 0)<=adc_data(11 downto 0);
-                                                       --adc_channels(11 downto 0)<=(others=>'0');
+                                                       adc_address<="001";     --ch0 address
                                                        channel:=ch0;
                                        end case;
                                end if;
@@ -196,7 +189,6 @@ begin
                                state<=f15;
                        when f15=>
                                adc_sclk<='0';
-                               --for rising edge detection in next cycle
                                state<=r15;
                        when r15=> --15th rising edge
                                adc_sclk<='1';