adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels
adc_sclk: out std_logic; --spi clk
adc_scs: out std_logic; --spi slave select
- adc_mosi: out std_logic --spi master out slave in
+ adc_mosi: out std_logic; --spi master out slave in
+ measur_count: out std_logic_vector(8 downto 0) --number of accumulated measurments
);
end component;
signal adc_reset : std_logic;
- signal adc_channels: std_logic_vector(35 downto 0);
+ signal adc_channels: std_logic_vector(71 downto 0);
+ signal adc_m_count: std_logic_vector(8 downto 0);
signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
--signal pwm_in, pwm_dir_in: std_logic;
signal gpio_clk: std_logic;
- signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
+ signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
signal ce0_old: std_logic_vector(1 downto 0);
signal pwm_sync: std_logic;
signal pwm_en_p: std_logic_vector(1 to 3);
signal pwm_en_n: std_logic_vector(1 to 3);
+ signal pwm_sig: std_logic_vector(1 to 3);
signal income_data_valid: std_logic;
match => pwm_match(i),
count => pwm_count,
-- outputs
- out_p => pwm(i), --positive signal
+ out_p => pwm_sig(i), --positive signal
out_n => shdn(i) --reverse signal is in shutdown mode
);
end generate;
adc_channels => adc_channels,
adc_sclk => adc_sclk,
adc_scs => adc_scs,
- adc_mosi => adc_mosi
+ adc_mosi => adc_mosi,
+ measur_count => adc_m_count
);
rs485_dir <= '0';
- --shdn(1) <= '0';
- --shdn(2) <= '1';
- --shdn(3) <= '0';
-
- --pwm(1) <= '0';
- --pwm(2) <= '0';
- --pwm(3) <= '0';
+ pwm(1) <= pwm_sig(1) and dip_sw(1);
+ pwm(2) <= pwm_sig(2) and dip_sw(2);
+ pwm(3) <= pwm_sig(3) and dip_sw(3);
+
+
process
begin
if (gpio7 = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
- dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
+ dat_reg(127 downto 0) <= dat_reg(126 downto 0) & gpio10;
end if;
elsif (spiclk_old="10" ) then --falling edge, faze zapisu
if (gpio7 = '0') then
- gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
+ gpio9 <= dat_reg(127); --zapisujeme nejdriv MSB
end if;
end if;
--sestupna hrana SS, pripravime data pro prenos
if (ce0_old = "10" ) then
income_data_valid<='0';
- dat_reg(95 downto 64) <= position(31 downto 0); --pozice
- dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
- dat_reg(60 downto 58) <= pwm_en_p(1 to 3); --enable positive
- dat_reg(57 downto 55) <= pwm_en_n(1 to 3); --shutdown
- dat_reg(54 downto 49) <= pwm_match(1)(10 downto 5); --6 MSb of PWM1
- dat_reg(48 downto 42) <= pwm_match(2)(10 downto 4); --7 MSb of PWM2
- dat_reg(41 downto 36) <= pwm_match(3)(10 downto 5); --6 MSb of PWM3
- dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
+ dat_reg(127 downto 96) <= position(31 downto 0); --pozice
+ dat_reg(95 downto 93) <= hal_in(1 to 3); --halovy sondy
+ dat_reg(92 downto 90) <= pwm_en_p(1 to 3); --enable positive
+ dat_reg(89 downto 87) <= pwm_en_n(1 to 3); --shutdown
+ dat_reg(86 downto 81) <= (others=>'0');--pwm_match(1)(10 downto 5); --6 MSb of PWM1
+ dat_reg(80 downto 72) <=adc_m_count(8 downto 0); --count of measurments
+ --data order schould be: ch2 downto ch0 downto ch1
+ dat_reg(71 downto 0) <= adc_channels(71 downto 0); --current mesurments
adc_reset<='0'; --remove reset flag, and wait on its rising edge
elsif (ce0_old = "01") then --rising edge of SS, we should read the data
adc_reset<='1';
- pwm_en_p(1 to 3)<=dat_reg(94 downto 92);
- pwm_en_n(1 to 3)<=dat_reg(91 downto 89);
+ pwm_en_p(1 to 3)<=dat_reg(126 downto 124);
+ pwm_en_n(1 to 3)<=dat_reg(123 downto 121);
--11 bit pwm TODO: make it generic
- pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(34 downto 24);
- pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(23 downto 13);
+ pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(66 downto 56);
+ pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(55 downto 45);
-- 12 + 11 Unused
- pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(10 downto 0);
+ pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(42 downto 32);
income_data_valid<='1';
end if;
end process;