PMSM design: use signals with descriptive names for pins connected to RPi SPI.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index f8e8bd5e6ef3c80aa141f6e6f96ec60df9cee125..3f8619423f93ac241749c098b19ee693babccc5a 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -170,7 +170,10 @@ architecture behavioral of rpi_pmsm_control is
        signal reset_sync, reset_async: std_logic;
        signal failsafe, next_failsafe: std_logic;
 
+       --RPi SPI interface signals named aliases
+       signal spi_clk, spi_ce, spi_mosi, spi_miso : std_logic;
        signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
+
        --signal pwm_in, pwm_dir_in: std_logic;
        signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
@@ -289,7 +292,7 @@ begin
                
        );
 
-       dummy_unused <= gpio2 and gpio3  and gpio4 and
+       dummy_unused <= gpio2 and gpio3 and
                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
                gpio15 and gpio16 and gpio19 and
@@ -303,12 +306,16 @@ begin
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
                irc_a and irc_b and
                gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
-               gpio8  and gpio11 and gpio7 and gpio10 and
+               gpio8  and
                ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
                        
        rs485_txd <= '1';
        rs485_dir <= '0';
 
+       spi_clk <= gpio11;
+       spi_ce <= gpio7;
+       spi_mosi <= gpio10;
+       gpio9 <= spi_miso;
 
        pwm(1) <= pwm_sig(1) and dip_sw(1);
        pwm(2) <= pwm_sig(2) and dip_sw(2);
@@ -343,22 +350,22 @@ begin
                wait until (gpio_clk'event and gpio_clk='1');
                
                --SCLK edge detection
-               spiclk_old(0)<=gpio11;
+               spiclk_old(0)<=spi_clk;
                spiclk_old(1)<=spiclk_old(0);
                
                --SS edge detection
-               ce0_old(0)<=gpio7;
+               ce0_old(0)<=spi_ce;
                ce0_old(1)<=ce0_old(0);
                
                if (spiclk_old="01") then --rising edge, faze cteni
-                       if (gpio7 = '0') then             -- SPI CS must be selected
+                       if (spi_ce = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
-                               dat_reg(127 downto 0) <= dat_reg(126 downto 0) & gpio10;
+                               dat_reg(127 downto 0) <= dat_reg(126 downto 0) & spi_mosi;
                                end if;
                elsif (spiclk_old="10" ) then --falling edge, faze zapisu
-                       if (gpio7 = '0') then
-                               gpio9 <= dat_reg(127); --zapisujeme nejdriv MSB
+                       if (spi_ce = '0') then
+                               spi_miso <= dat_reg(127); --zapisujeme nejdriv MSB
                        end if;
                end if;