Added ADC reset after each FPGA<->RPi transfer. ADC channels manipulation improved.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index fdfe6260b8da26d9e10ded8ecce33ebdc1ace1d0..1e06af923d5c14d9c8e8a32111afc01c16d406b8 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -351,7 +351,7 @@ begin
                        dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
                        adc_reset<='0'; --remove reset flag, and wait on its rising edge
                elsif (ce0_old = "01") then --rising edge of SS, we should read the data
-                       adc_reset<=dat_reg(95);
+                       adc_reset<='1';
                        pwm_en_p(1 to 3)<=dat_reg(94 downto 92);
                        pwm_en_n(1 to 3)<=dat_reg(91 downto 89);
                        --11 bit pwm TODO: make it generic