Bug fix: unconsistent changes of match signal caused twitches im motor movement....

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 413f11c297fff1499e8df1aa55c2e6a2d6789ffc..beb4b9cfd2fa1fc291ec6681fad2264996f04961 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -167,7 +167,6 @@ architecture behavioral of rpi_pmsm_control is
        end component;
        
        
-       signal adc_reset : std_logic;
        signal adc_channels: std_logic_vector(71 downto 0);
        signal adc_m_count: std_logic_vector(8 downto 0);
 
@@ -198,6 +197,7 @@ architecture behavioral of rpi_pmsm_control is
        
        signal pwm_match: pwm_res_type;                                 --point of reversion of pwm output, 0 to 2047
        signal pwm_count: std_logic_vector (pwm_width-1 downto 0);      --counter, 0 to 2047
+       signal pwm_sync_at_next: std_logic;
        signal pwm_sync: std_logic;
        signal pwm_en_p: std_logic_vector(1 to 3);
        signal pwm_en_n: std_logic_vector(1 to 3);
@@ -262,7 +262,7 @@ begin
                port map (
                        clock => gpio_clk,                              --50 Mhz clk from gpclk on raspberry
                        sync => pwm_sync,                               --counter restarts
-                       data_valid => income_data_valid,                        
+                       data_valid => pwm_sync_at_next,                 
                        failsafe => failsafe,
                        --
                        -- pwm config bits & match word
@@ -293,7 +293,7 @@ begin
        port map(
                clk => gpio_clk,
                divided_clk => clk_4M17,
-               adc_reset => adc_reset,
+               adc_reset => income_data_valid, --reset at each SPI cycle,TODO: replace with PLL reset
                adc_miso => adc_miso,
                adc_channels => adc_channels,
                adc_sclk => adc_sclk,
@@ -345,8 +345,16 @@ begin
        process
        begin
                wait until (gpio_clk'event and gpio_clk='1');
-               IF(pwm_count = pwm_period) THEN                         
-               --end of period reached
+               IF pwm_count = std_logic_vector(unsigned(pwm_period) - 1) THEN                          
+                       --end of period nearly reached
+                       --fetch new pwm match data
+                       pwm_sync_at_next <= '1';
+               else
+                       pwm_sync_at_next <= '0';
+               end if;
+               
+               if pwm_sync_at_next='1' then
+                       --end of period reached
                        pwm_count <= (others=>'0');      --reset counter
                        pwm_sync <= '1';                                -- inform PWM logic about new period start
                ELSE                                                    --end of period not reached
@@ -391,16 +399,13 @@ begin
                        --data order schould be: ch2 downto ch0 downto ch1
                        dat_reg(71 downto 0) <= adc_channels(71 downto 0);      --current mesurments
                        spi_miso <= position(31);               --prepare the first bit on SE activation
-                       adc_reset<='0'; --remove reset flag, and wait on its rising edge
                elsif (ce0_old = "01") then --rising edge of SS, we should read the data
-                       adc_reset<='1';
                        pwm_en_p(1 to 3)<=dat_reg(126 downto 124);
                        pwm_en_n(1 to 3)<=dat_reg(123 downto 121);
-                       --11 bit pwm TODO: make it generic
-                       pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(66 downto 56);
-                       pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(55 downto 45);
-                       -- 12 + 11 Unused
-                       pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(42 downto 32);
+                       --usable for up to 16-bit PWM duty cycle resolution (pwm_width):
+                       pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(pwm_width+31 downto 32);
+                       pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(pwm_width+15 downto 16);
+                       pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(pwm_width-1 downto 0);
                        income_data_valid<='1';
                end if;
        end process;