component adc_reader is
port (
clk: in std_logic; --input clk
+ divided_clk : in std_logic; --divided clk - value suitable to sourcing voltage
adc_reset: in std_logic;
adc_miso: in std_logic; --spi master in slave out
adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels
-- while we use +3.3V Vcc
adc_reader_map: adc_reader
port map(
- clk =>clk_4M17,
+ clk => gpio_clk,
+ divided_clk => clk_4M17,
adc_reset => adc_reset,
adc_miso => adc_miso,
adc_channels => adc_channels,
dat_reg(80 downto 72) <=adc_m_count(8 downto 0); --count of measurments
--data order schould be: ch2 downto ch0 downto ch1
dat_reg(71 downto 0) <= adc_channels(71 downto 0); --current mesurments
+ spi_miso <= position(31); --prepare the first bit on SE activation
adc_reset<='0'; --remove reset flag, and wait on its rising edge
elsif (ce0_old = "01") then --rising edge of SS, we should read the data
adc_reset<='1';