--
--- * LXPWR slave part *
--- common sioreg & common counter for several ADC&PWM blocks
+-- * Raspberry Pi BLDC/PMSM motor control design for RPi-MI-1 board *
+-- The toplevel component file
--
--- part of LXPWR motion control board (c) PiKRON Ltd
--- idea by Pavel Pisa PiKRON Ltd <pisa@cmp.felk.cvut.cz>
--- code by Marek Peca <mp@duch.cz>
--- 01/2013
+-- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
+-- Czech Technical University in Prague
--
--- license: GNU GPLv3
+-- Project supervision and original project idea
+-- idea by Pavel Pisa <pisa@cmp.felk.cvut.cz>
+--
+-- Related RPi-MI-1 hardware is designed by Petr Porazil,
+-- PiKRON Ltd <http://www.pikron.com>
+--
+-- VHDL design reuses some components and concepts from
+-- LXPWR motion power stage board and LX_RoCoN system
+-- developed at PiKRON Ltd with base code implemented
+-- by Marek Peca <hefaistos@gmail.com>
+--
+-- license: GNU LGPL and GPLv3+
--
library ieee;
component adc_reader is
port (
clk: in std_logic; --input clk
+ divided_clk : in std_logic; --divided clk - value suitable to sourcing voltage
adc_reset: in std_logic;
adc_miso: in std_logic; --spi master in slave out
adc_channels: out std_logic_vector (35 downto 0); --consistent data of 3 channels
end component;
- signal adc_reset : std_logic;
signal adc_channels: std_logic_vector(71 downto 0);
signal adc_m_count: std_logic_vector(8 downto 0);
signal reset_sync, reset_async: std_logic;
signal failsafe, next_failsafe: std_logic;
+ --RPi SPI interface signals named aliases
+ signal spi_clk, spi_ce, spi_mosi, spi_miso : std_logic;
signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
+
--signal pwm_in, pwm_dir_in: std_logic;
signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
signal pwm_match: pwm_res_type; --point of reversion of pwm output, 0 to 2047
signal pwm_count: std_logic_vector (pwm_width-1 downto 0); --counter, 0 to 2047
+ signal pwm_sync_at_next: std_logic;
signal pwm_sync: std_logic;
signal pwm_en_p: std_logic_vector(1 to 3);
signal pwm_en_n: std_logic_vector(1 to 3);
signal income_data_valid: std_logic;
signal clk_4M17: std_logic;
-
-
+
+ -- irc signals processing
+ signal irc_i_prev: std_logic;
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
port map (
clock => gpio_clk, --50 Mhz clk from gpclk on raspberry
sync => pwm_sync, --counter restarts
- data_valid => income_data_valid,
+ data_valid => pwm_sync_at_next,
failsafe => failsafe,
--
-- pwm config bits & match word
-- while we use +3.3V Vcc
adc_reader_map: adc_reader
port map(
- clk =>clk_4M17,
- adc_reset => adc_reset,
+ clk => gpio_clk,
+ divided_clk => clk_4M17,
+ adc_reset => income_data_valid, --reset at each SPI cycle,TODO: replace with PLL reset
adc_miso => adc_miso,
adc_channels => adc_channels,
adc_sclk => adc_sclk,
);
- dummy_unused <= gpio2 and gpio3 and gpio4 and
+ dummy_unused <= gpio2 and gpio3 and
gpio5 and gpio6 and
gpio12 and gpio13 and gpio14 and
gpio15 and gpio16 and gpio19 and
dip_sw(1) and dip_sw(2) and dip_sw(3) and
irc_a and irc_b and
gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
- gpio8 and gpio11 and gpio7 and gpio10 and
+ gpio8 and
ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
rs485_txd <= '1';
rs485_dir <= '0';
+ spi_clk <= gpio11;
+ spi_ce <= gpio7;
+ spi_mosi <= gpio10;
+ gpio9 <= spi_miso;
pwm(1) <= pwm_sig(1) and dip_sw(1);
pwm(2) <= pwm_sig(2) and dip_sw(2);
process
begin
- wait until (irc_i'event and irc_i='1');
- index_position(11 downto 0)<=position(11 downto 0);
+ wait until (gpio_clk'event and gpio_clk='1');
+ if irc_i_prev = '0' and irc_i = '1' then
+ index_position(11 downto 0)<=position(11 downto 0);
+ end if;
+ irc_i_prev<=irc_i;
end process;
process
begin
wait until (gpio_clk'event and gpio_clk='1');
- IF(pwm_count = pwm_period) THEN
- --end of period reached
+ IF pwm_count = std_logic_vector(unsigned(pwm_period) - 1) THEN
+ --end of period nearly reached
+ --fetch new pwm match data
+ pwm_sync_at_next <= '1';
+ else
+ pwm_sync_at_next <= '0';
+ end if;
+
+ if pwm_sync_at_next='1' then
+ --end of period reached
pwm_count <= (others=>'0'); --reset counter
pwm_sync <= '1'; -- inform PWM logic about new period start
ELSE --end of period not reached
wait until (gpio_clk'event and gpio_clk='1');
--SCLK edge detection
- spiclk_old(0)<=gpio11;
+ spiclk_old(0)<=spi_clk;
spiclk_old(1)<=spiclk_old(0);
--SS edge detection
- ce0_old(0)<=gpio7;
+ ce0_old(0)<=spi_ce;
ce0_old(1)<=ce0_old(0);
if (spiclk_old="01") then --rising edge, faze cteni
- if (gpio7 = '0') then -- SPI CS must be selected
+ if (spi_ce = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
- dat_reg(127 downto 0) <= dat_reg(126 downto 0) & gpio10;
+ dat_reg(127 downto 0) <= dat_reg(126 downto 0) & spi_mosi;
end if;
elsif (spiclk_old="10" ) then --falling edge, faze zapisu
- if (gpio7 = '0') then
- gpio9 <= dat_reg(127); --zapisujeme nejdriv MSB
+ if (spi_ce = '0') then
+ spi_miso <= dat_reg(127); --zapisujeme nejdriv MSB
end if;
end if;
dat_reg(80 downto 72) <=adc_m_count(8 downto 0); --count of measurments
--data order schould be: ch2 downto ch0 downto ch1
dat_reg(71 downto 0) <= adc_channels(71 downto 0); --current mesurments
- adc_reset<='0'; --remove reset flag, and wait on its rising edge
+ spi_miso <= position(31); --prepare the first bit on SE activation
elsif (ce0_old = "01") then --rising edge of SS, we should read the data
- adc_reset<='1';
pwm_en_p(1 to 3)<=dat_reg(126 downto 124);
pwm_en_n(1 to 3)<=dat_reg(123 downto 121);
- --11 bit pwm TODO: make it generic
- pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(66 downto 56);
- pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(55 downto 45);
- -- 12 + 11 Unused
- pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(42 downto 32);
+ --usable for up to 16-bit PWM duty cycle resolution (pwm_width):
+ pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(pwm_width+31 downto 32);
+ pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(pwm_width+15 downto 16);
+ pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(pwm_width-1 downto 0);
income_data_valid<='1';
end if;
end process;
projects / fpga / rpi-motor-control.git / blobdiff