Little changes to get rid of warnings.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index 56401e50c76c73b2106fb374747ca136d666cb43..11f97afece3a11e430a13e36a3067b572180e59a 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -22,15 +22,15 @@ port (
        gpio4: in std_logic; -- CLK
        gpio14: in std_logic; -- Tx
        gpio15: in std_logic; -- Rx
-       gpio17: out std_logic; -- RTS
-       gpio18: out std_logic; -- PWM0/PCMCLK
-       gpio27: out std_logic; -- SD1DAT3
-       gpio22: out std_logic; -- SD1CLK
-       gpio23: out std_logic; -- SD1CMD
-       gpio24: out std_logic; -- SD1DAT0
+       gpio17: in std_logic; -- RTS
+       gpio18: in std_logic; -- PWM0/PCMCLK
+       gpio27: in std_logic; -- SD1DAT3
+       gpio22: in std_logic; -- SD1CLK
+       gpio23: in std_logic; -- SD1CMD
+       gpio24: in std_logic; -- SD1DAT0
        gpio10: in std_logic; -- SPI0MOSI
        gpio9: out std_logic; -- SPI0MISO
-       gpio25: out std_logic; -- SD1DAT1
+       gpio25: in std_logic; -- SD1DAT1
        gpio11: in std_logic; -- SPI0SCLK
        gpio8: in std_logic; -- SPI0CE0
        gpio7: in std_logic; -- SPI0CE1
@@ -115,6 +115,9 @@ architecture behavioral of rpi_mc_simple_dc is
 
        type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,reset);
        signal state : state_type;
+       
+       type channel_type is (ch0, ch1, ch2);
+       
        signal adc_data: std_logic_vector(11 downto 0); --ADC income data
        signal adc_reset : std_logic;
        signal adc_rst_old : std_logic_vector(1 downto 0);
@@ -122,7 +125,7 @@ architecture behavioral of rpi_mc_simple_dc is
        signal adc_channels: std_logic_vector(35 downto 0);
        
        signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
-       signal pwm_in, pwm_dir_in: std_logic;
+       --signal pwm_in, pwm_dir_in: std_logic;
        signal gpio_clk: std_logic;
        signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
@@ -186,7 +189,7 @@ begin
                can_rx and can_tx and
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
                irc_a and irc_b and
-               -- gpio17 and gpio18 and gpio27 and gpio22 and
+               gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
                gpio8  and gpio11 and gpio7 and gpio10 and
                ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
                        
@@ -242,17 +245,18 @@ begin
        
        process 
                variable data_ready : std_logic;
-               variable channel: std_logic_vector(1 downto 0);
+               variable channel: channel_type;
        begin
                wait until (gpio_clk'event and gpio_clk='1');
                case state is
                        when reset=>
-                               adc_scs<='0'; --active-high SS
+                               adc_scs<='1'; --active-high SS
                                data_ready:='0';
                                --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
                                adc_address<="001101010";
-                               channel:="00";
+                               channel:=ch0;
                        when f1=>
+                               adc_scs<='0'; --active-high SS
                                adc_sclk<='0'; --clk
                                adc_mosi<='1'; --start bit
                                state<=r1; --next state
@@ -310,15 +314,15 @@ begin
                                adc_sclk<='1';
                                if (data_ready='1') then
                                        case channel is
-                                               when "00"=>
+                                               when ch0=>
                                                        adc_channels(35 downto 24)<=adc_data(11 downto 0);
-                                                       channel:="01";
-                                               when "01"=>
+                                                       channel:=ch1;
+                                               when ch1=>
                                                        adc_channels(23 downto 12)<=adc_data(11 downto 0);
-                                                       channel:="10";
-                                               when "10"=>
+                                                       channel:=ch2;
+                                               when ch2=>
                                                        adc_channels(11 downto 0)<=adc_data(11 downto 0);
-                                                       channel:="00";
+                                                       channel:=ch0;
                                        end case;
                                end if;
                                data_ready:='1';
@@ -367,12 +371,13 @@ begin
                                state<=f14;
                        when f14=>
                                adc_sclk<='0';
+                               --for rising edge detection in next cycle
+                               adc_rst_old(0)<=adc_reset;
+                               adc_rst_old(1)<=adc_rst_old(0);
                                state<=r14;
                        when r14=> --15th rising edge
                                adc_sclk<='1';
                                adc_data(6)<=adc_miso;
-                               adc_rst_old(0)<=adc_reset;
-                               adc_rst_old(1)<=adc_rst_old(0);
                                if (adc_rst_old="01") then --we check rising edge of reset 
                                        state<=reset;
                                else