Added synchronous detection o divided clk signal to adc_reader component.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 2127d2e93554f937e4c39db52f6a437f94a7aa38..413f11c297fff1499e8df1aa55c2e6a2d6789ffc 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -154,6 +154,7 @@ architecture behavioral of rpi_pmsm_control is
        component adc_reader is
        port (
                clk: in std_logic;                                      --input clk
+               divided_clk : in std_logic;                             --divided clk - value suitable to sourcing voltage
                adc_reset: in std_logic;
                adc_miso: in std_logic;                                 --spi master in slave out
                adc_channels: out std_logic_vector (35 downto 0);       --consistent data of 3 channels
@@ -290,7 +291,8 @@ begin
        --        while we use +3.3V Vcc     
        adc_reader_map: adc_reader 
        port map(
-               clk =>clk_4M17,
+               clk => gpio_clk,
+               divided_clk => clk_4M17,
                adc_reset => adc_reset,
                adc_miso => adc_miso,
                adc_channels => adc_channels,