library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.util.all; entity div8 is port ( clk_in: in std_logic; clk_out: out std_logic ); end div8; architecture behavioral of div8 is signal count : std_logic_vector (2 downto 0); begin divider : process begin wait until (clk_in'event and clk_in='1'); if (count="111") then count<="000"; else count <= std_logic_vector(unsigned(count) + 1); end if; clk_out <= count(2); end process divider; end behavioral;